The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.

A semiconductor module includes a heat sink configured to conduct a cooling fluid in a cooling-fluid flow direction. A first semiconductor assembly is arranged on a surface of the heat sink. The first semiconductor assembly includes a first substrate having a first dielectric material layer, and a first semiconductor element connected to the first substrate. A second semiconductor assembly is arranged on the surface of the heat sink and closest to a downstream end of the heat sink. The second semiconductor assembly includes a second substrate having a second dielectric material layer, and a second semiconductor element connected to the second substrate. The second dielectric material layer has a thermal conductivity which is higher than a thermal conductivity of the first dielectric material layer.

An image sensor includes a stack structure including an active pixel region of pixels, and a pad region. The stack structure further includes a first substrate including a photoelectric conversion region and a floating diffusion region, a first semiconductor substrate, a first front structure arranged on a first surface of the first semiconductor substrate, a second substrate attached to the first front structure and including pixel gates, a second semiconductor substrate, and a second front structure, a third substrate attached to the second substrate and including a logic transistor for driving the pixels, and a pad arranged in the pad region. A side surface and a bottom surface of the pad are surrounded by the second front structure, and at least a portion of a top surface of the pad is exposed through a pad opening penetrating the first substrate and extending into the second substrate.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

A semiconductor chip including a semiconductor substrate having first and second surfaces, a transistor on the first surface, a first interlayer dielectric layer on the transistor, a second interlayer dielectric layer on the first interlayer dielectric layer, a wiring line in the second interlayer dielectric layer, a first conductive pad on the second interlayer dielectric layer, a first passivation layer on the second interlayer dielectric layer, a second conductive pad in the first passivation layer, a through via penetrating the semiconductor substrate and the first interlayer dielectric layer to come into connection with the wiring line, a second passivation layer on the second surface, and a third conductive pad in the second passivation layer and connected to the through via. The first passivation layer has a first thickness 0.4 to 0.6 times a second thickness between the first surface and a top surface of the second passivation layer.

A stacked semiconductor device includes first chips and a second chip. The first chips are arranged in an array, and includes first and second type through vias, an internal wire layer, a redistribution line and conductive pins. The internal wire layer is disposed on and electrically connected to the first and second type through vias. The redistribution line is disposed on and electrically connected to the second type through vias and the internal wire layer, wherein the redistribution line extends from a top surface of the second type through vias to a position non-overlapped with the second type through vias. The conductive pins are disposed on and electrically connected to the redistribution line. The second chip is stacked on the first chips, wherein the second chip includes connection pins, and the second chip is connected to the first chips by bonding the connection pins to the conductive pins.

A display module is disclosed. The display module includes a substrate; a plurality of inorganic light-emitting diodes provided in a plurality of mounting grooves formed in the substrate, the plurality of inorganic light-emitting diodes including an inorganic light-emitting diode that has a first chip electrode and a second chip electrode; a first substrate electrode pad and a second substrate electrode pad provided at a bottom surface of a mounting groove from among the plurality of mounting grooves, the first substrate electrode pad being electrically coupled to the first chip electrode and the second substrate electrode pad being electrically coupled to the second chip electrode; and a third substrate electrode pad and a fourth substrate electrode pad provided around the mounting groove.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.