The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

A semiconductor device according to the present invention includes a first conductive-type Sic semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Microelectronic assemblies may include through-assembly conductive vias of varying depth to couple dies or die stacks with one another via a bridge die and/or substrate. In one example, an assembly includes an interconnect structure (e.g., a bridge die) including conductive contacts on a first side and one or more integrated circuit (IC) structures bonded with a second side, where an IC structure includes one or more dies. The assembly may include a first conductive via with a first bottom end in the interconnect structure and a first top end opposite the first bottom end, and a second conductive via with a second bottom end in the interconnect structure and a second top end opposite the second bottom end, where the first top end is in a first plane and the second top end is in a second plane that is different from the first plane.

A device comprising a memory device comprising a first memory chip comprising a first memory portion; and a first processor in memory portion, wherein the first processor in memory portion includes a first plurality of logic cells and at least one first capacitor; and a second memory chip coupled to the first memory chip.

A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

A semiconductor device includes semiconductor elements. Each semiconductor element, including first, second and third electrodes, is controlled to turn on and off current flow between the first electrode and the second electrode by drive signals inputted to the third electrode. The first electrodes of the semiconductor elements are electrically connected mutually, and the second electrodes of the semiconductor elements are electrically connected mutually. The semiconductor device further includes a control terminal receiving the drive signals, a first wiring section connected to the control terminal, a second wiring section, and third wiring sections, and further a first connecting member electrically connecting the first and the second wiring sections, a second connecting member electrically connecting the second wiring section and each third wiring section, and third connecting members connecting the third wiring sections and the third electrodes of the semiconductor elements.

A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.