A semiconductor package is provided. The semiconductor package comprises a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is smaller than a width of the second bonding layer in the horizontal direction, wherein the width of the second bonding layer in the horizontal direction is greater than a width of the first semiconductor die in the horizontal direction.

A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes: one or more electronic components; a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; main surfaces and side surfaces, wherein the main surfaces of adjacent chiplets of the plurality of chiplets face each other. The device may further include an electrically conductive connection formed on at least one side surface of at least one chiplet of the plurality of chiplets to electrically connect one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.

A semiconductor package comprises: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer comprising an interconnection pattern; and a bonding pad on a bottom surface of the interconnection pattern, wherein the bonding pad is directly bonded to the first pad, wherein a width of the interconnection pattern is larger than a width of the bonding pad, wherein a width of the first conductive pattern is smaller than a width of the first pad, and wherein the interconnection pattern and the bonding pad comprise different materials.

A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.

A metal film, a manufacturing method of the metal film, semiconductor device, and a manufacturing method of semiconductor device are provided with high crack resistance (higher hardness) during wire bonding. The Metal film has first metal crystal grains, and the second metal crystal grains. Each of the first metal crystal grains has dislocations. Each of the second metal crystal grains has no dislocations. The number of the first metal crystal grains having the dislocations is larger than the number of the second metal crystal grains having no dislocations.

A semiconductor package includes a first semiconductor chip having a first front surface and a first back surface opposing each other, and including first front connection pads, first back connection, and through-electrodes, a second semiconductor chip having a second front surface facing the first back surface and including second front connection pads, a substrate having a third back surface facing the first front surface and including upper pads and lower pads disposed opposite to each other, first bump structures between the first semiconductor chip and the second semiconductor, second bump structures between the first semiconductor chip and the substrate, and connection bumps. A first gap between the second front surface and the first back surface is equal to or greater than a second gap between the first front surface and the third back surface, and the second gap is greater than a thickness of the first semiconductor chip.

A semiconductor package includes a buffer die, middle core dies stacked in a vertical direction on the buffer die, a top core die on an uppermost one of the middle core die, dummy dies stacked in the vertical direction on the top core die, a first bonding layer structure between the middle core dies and including a first bonding pad structure, a second bonding layer structure between the top core and a lowermost one of the dummy dies, and a third bonding layer structure between the dummy dies.