A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

A semiconductor structure including a first structure of a first wafer including a first substrate layer, a first device layer disposed on the first substrate layer, a first bonding layer disposed on the first device layer including a first portion of an alignment mark, and a second structure of a second wafer including a second substrate layer, a second device layer disposed on the second substate layer, a second bonding layer disposed on the second device layer including a second portion of the alignment mark, wherein the first portion of the alignment mark and the second portion of the alignment mark forms the alignment mark configured to provide an alignment for bonding cross the first bonding layer and the second bonding layer. The first device layer or the second device layer may include a three-dimensional NAND flash memory circuit as a part of a storage media with high-performance and high-capacity.

Embodiments disclosed herein include semiconductor devices. In an embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment a fiducial is on the substrate. In an embodiment, the fiducial is a cantilever beam that extends out past an edge of the substrate.

The disclosure provides a method of manufacturing an electronic device. The method of manufacturing the electronic device includes the following steps: providing a transparent carrier having an accommodation space, wherein the transparent carrier has a first mark; disposing a sample in the accommodation space of the transparent carrier, wherein the sample has a second mark; calculating an offset of the sample according to the first mark, the second mark, and a standard value; and forming a third mark on the sample or the transparent carrier according to the offset. The method of manufacturing of the electronic device of the disclosure may improve process yield or reliability.

An electronic device is provided. The electronic device includes a plurality of conductive elements, a first electronic unit and a protective layer. The first electronic unit is disposed between two adjacent first conductive elements of the plurality of conductive elements. A second conductive element of the plurality of conductive elements is disposed adjacent to one of the two adjacent first conductive elements of the plurality of conductive elements. The protective layer surrounds the plurality of conductive elements and the first electronic unit. Moreover, the one of the two adjacent first conductive elements has a first width, the second conductive element has a second width, and the second width is less than the first width.

A bonding apparatus and a bonding method are provided. The bonding apparatus includes: a machine base, including a movable pick-up platform; and a grating assembly, configured to determine displacement information of the movable pick-up platform along a first direction and displacement information of the movable pick-up platform along a second direction. Based on the displacement information along the first direction and the displacement information along the second direction, the grating assembly is further configured to determine coordinate information of the movable pick-up platform.

A semiconductor substrate includes a semiconductor base substrate. An alignment structure is formed on a surface of the semiconductor base substrate. An epitaxial layer is deposited on the surface of the semiconductor base substrate. The alignment structure includes an area of the surface of the semiconductor base substrate that is formed as a groove pattern. Grooves of the groove pattern are aligned with a specific crystallographic direction of the semiconductor base substrate. The specific crystallographic direction provides for a slower epitaxial growth rate on such a groove-patterned base substrate surface area compared to epitaxial growth on a surface of the semiconductor base substrate adjacent to the groove-patterned area.

A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

A semiconductor package includes a package substrate, a first chip group including at least one first chip spaced apart from the package substrate in a first direction perpendicular to a surface of the package substrate, a second chip group including at least one second chip disposed between the package substrate and the first chip group, a first molding film that surrounds the first chip group, a second molding film that surrounds the second chip group, and an alignment post that penetrates the first molding film and contacts the second molding film. The second molding film covers a surface of an end portion of the alignment post facing the package substrate.

Apparatus and methods for determining wafer characters are disclosed. In one example, an apparatus is disclosed. The apparatus includes: a processing tool configured to process a semiconductor wafer; a device configured to read an optical character disposed on the semiconductor wafer while the semiconductor wafer is located at the apparatus for wafer fabrication; and a controller configured to determine whether the optical character matches a predetermined character corresponding to the semiconductor wafer based on the optical character read in real-time at the apparatus.