In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

A printed circuit board includes a substrate base; a plurality of ball lands arranged on a surface of the substrate base; a cutting position identification mark disposed on a corner of the surface of the substrate base; and at least one alignment mark disposed on the surface of the substrate base to be spaced apart from the ball lands and exposed to the outside, wherein top surfaces of the ball lands and a top surface of the at least one alignment mark are at substantially the same vertical level and the ball lands and the at least one alignment mark include the same material.

A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.

Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

A semiconductor module includes a semiconductor element, a case configured to house the semiconductor element, and a plurality of control terminal units. Each of the control terminal units includes at least one control terminal electrically connected to the semiconductor element, and a guide block constituted of a separate component from the case fixed integrally to the at least one control terminal. The at least one control terminal each includes a terminal pin part protruding from an outer wall surface of the case. Each of the guide blocks includes a guide pin part protruding from the outer wall surface of the case in a direction the same as the direction in which the terminal pin part protrudes. The guide blocks of the control terminal units are constituted of separate components.

Embodiments provide a semiconductor device and a fabrication method. The fabrication method includes: providing a substrate including an alignment region and a connection region; forming a first conductive layer on the substrate; forming a spacer material layer group on the first conductive layer; forming a protective layer on the spacer material layer group, the protective layer being positioned on the alignment region; etching the spacer material layer group and the protective layer, an etching rate of the protective layer being less than an etching rate of the spacer material layer group to remove the spacer material layer group on the connection region to form a spacer layer group, and forming an alignment groove on the spacer layer group in the alignment region; and forming a second conductive layer group on the spacer layer group and the first conductive layer, the second conductive layer group covering the alignment groove.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

Provided is a method of manufacturing a substrate including an alignment mark, including: forming the alignment mark and a recess portion on the substrate, the alignment mark not penetrating the substrate and including a bottom portion with a lower infrared transmittance than that of a first surface and a second surface of the substrate; and aligning the substrate by orthogonally arranging predetermined positions of the first surface and the second surface of the substrate in a horizontal direction and an infrared ray camera and by image-identifying the alignment mark formed on the substrate with transmitted light of infrared rays emitted from the infrared ray camera.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.