A semiconductor package includes a redistribution structure including a first redistribution layer, a semiconductor chip on the redistribution structure and having a contact pad electrically connected to the first redistribution layer, a vertical connection conductor on the redistribution structure and electrically connected to the first redistribution layer, a molding portion disposed on the redistribution structure, a second redistribution layer disposed on the molding portion, connected to the vertical connection conductor, and having a plurality of first pads, each of the plurality of first pads having an alignment hole, a plurality of second pads respectively disposed on the plurality of first pads and having a side portion covering an inner sidewall of the alignment hole, the alignment hole having an inner space surrounded by the side portion, and a protective insulating layer covering the second redistribution layer, and having a plurality of contact openings respectively exposing the plurality of second pads.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

A memory device may include a substrate, a lower electrode disposed on the substrate in a chip region, an upper electrode on the lower electrode, a dielectric layer disposed between the lower electrode and the upper electrode, a dummy upper electrode disposed over the substrate in a scribe lane region continuous with the chip region, and disposed at a level higher than an upper surface of the lower electrode, and an alignment key disposed on the dummy upper electrode.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

The invention provides an overlay mark, which comprises four sub-overlay marks, which together form an overlay mark, wherein each sub-overlay mark comprises a substrate and defines an inner region and an outer region, a plurality of first mandrel structures located in the inner region and a plurality of second mandrel structures located in the outer region, wherein the first mandrel structures are arranged in parallel with each other, and the second mandrel structures are also arranged in parallel with each other, and a plurality of strip-shaped mask layers are located in the inner region, wherein both sides of any first mandrel structure comprise a strip-shaped mask layer respectively. In addition, the invention also provides an overlay method of the semiconductor structure using the overlay mark.

Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.

A die alignment method includes vertically aligning a first die comprising first magnetic patterns and a second die comprising second magnetic patterns with each other using magnetic force between the first magnetic patterns and the second magnetic patterns. Each of the first magnetic patterns and the second magnetic patterns comprises a horizontally magnetically anisotropic material. The first magnetic patterns and the second magnetic patterns do not vertically overlap each other when the first die and the second die are vertically aligned with each other.

A semiconductor package may include a lower semiconductor chip, a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, non-conductive layers between the lower semiconductor chip and a lowermost one of the semiconductor chips and between the semiconductor chips, a mold layer on the semiconductor chips and the non-conductive layers, and a vision layer on the mold layer. The vision layer may include a metallic material, and a bottom surface of the vision layer may be in contact with a top surface of the uppermost one of the semiconductor chips and a top surface of the mold layer.