A semiconductor package may include: a lower insulating layer including recess grooves recessed into the lower insulating layer from a top surface of the lower insulating layer; a first semiconductor chip on the lower insulating layer in a first vertical direction, and spaced apart from the recess grooves in at least one horizontal direction, the first semiconductor chip including a first through electrode; a second semiconductor chip on the first semiconductor chip in the first vertical direction; and a molding layer in contact with the top surface of the lower insulating layer, a side surface of the first semiconductor chip, and a side surface of the second semiconductor chip, wherein, in a plan view of the semiconductor package, a size of an area of the lower insulating layer is greater than a size of an area of the first semiconductor chip, and wherein portions of the molding layer are in the recess grooves of the lower insulating layer.

A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first wiring structure including a first wiring pattern and a first wiring insulating film, a second semiconductor chip including a second semiconductor substrate and a second wiring structure including a second wiring pattern and a second wiring insulating film, a first bonding pad on the first wiring structure, a first passivation layer surrounding a side surface of the first bonding pad, a second bonding pad electrically connected to the first bonding pad, a second passivation layer surrounding a side surface of the second bonding pad, a first alignment inspection structure horizontally apart from the first wiring pattern and penetrating the first passivation layer, and a second alignment inspection structure vertically penetrating the second semiconductor substrate, the second wiring insulating film, and the second passivation layer.

A mounting device includes: a bonding head configured to hold a first object, a bonding stage configured to hold a second object, and a dual-field-of-view (FOV) optical system including an image sensor configured to simultaneously capture an image of a first alignment mark on the first object and an image of a second alignment mark on the second object to obtain a first image. At least one of the bonding head and the bonding stage is configured to adjust a relative position between the first object and the second object based on the first image, and bond the first object to the second object.

A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction so that a chip is cut out from an effective area. The semiconductor water includes a film formation pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line which overlaps the film formation pattern in its entire or partial length.

A semiconductor device includes a substrate including a key region; dummy active structures on the key region, extending in a first direction parallel to an upper surface of the substrate, spaced apart from each other in a second direction perpendicular to the first direction, and each including at least one dummy active region; a dummy device isolation layer in the key region and defining the at least one dummy active region; and a dummy upper isolation structure on the dummy device isolation layer and a portion of each of the dummy active structures and including first patterns extending in the first direction.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A substrate includes: a first die alignment mark and a first die position mark defining a die stack region. The first die alignment mark has substantially a cross shape having substantially a vertical bar and substantially a horizontal bar intersecting each other substantially perpendicularly, and the first die position mark includes a first main position mark having a first area and a first branch position mark having a second area different from the first area.

A method for manufacturing a power device fabrication panel includes aligning a first alignment mark in a lead frame of a power device substrate array with a second alignment mark in a bonding fixture. The power device substrate array includes a plurality of power device pockets, the bonding fixture includes a plurality of power device openings, and the power device openings are in assembly alignment with the power device pockets when the first alignment mark is aligned with the second alignment mark. And with the bonding fixture power device openings in assembly alignment with the power device pockets of the power device substrate array, a plurality of power devices are moved at least partially through the aligned power device openings and into the power device pockets where they are bonded.

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.