In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

A semiconductor package includes a silicon substrate including a plurality of through openings, and a redistribution wiring layer including a first surface and a second surface opposite the first surface, the second surface facing the silicon substrate, the redistribution wiring layer including a first pad area and a second pad area. The redistribution wiring layer includes a plurality of bonding pads on the first pad area at the first surface, a plurality of test pads on the second pad area at the first surface, a plurality of landing pads on the second pad area at the second surface, the plurality of landing pads in communication with the plurality of through openings, respectively, and a plurality of redistribution wires electrically connected to the plurality of bonding pads and the plurality of landing pads.

A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.

A method of making a semiconductor assembly may include mounting a plurality of components to a patterned element on an intermediate carrier, and disposing an encapsulant over the intermediate carrier, where the encapsulant may be disposed around four side surfaces of each of the plurality of components and one or more of the plurality of components may comprise conductive studs disposed over a front surface of the components. The method may further include removing a portion of the encapsulant to form a planar surface above the front surface, wherein the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant. The method may further comprise removing the intermediate carrier through a grinding process, and terminating the grinding process when at least a portion of the patterned element is exposed.

A semiconductor structure and semiconductor device are provided. The semiconductor structure includes a plurality of layers of memory modules stacked on an upper surface of the logic chip in a first direction which is perpendicular to the upper surface of the logic chip. Each storage module includes a plurality of memory chips stacked in a second direction which is parallel to the upper surface. Each memory chip in a top layer includes one second wireless communication part; and each memory chip in a non-top layer includes two second wireless communication parts arranged in the first direction and a wired communication part connected between the two second wireless communication parts. Two adjacent second wireless communication parts located on different memory chips in the first direction communicate with each other wirelessly; and each first wireless communication part communicates wirelessly with a closest second wireless communication part in a bottom memory chip.

The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, a interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.

A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.

A semiconductor structure includes a semiconductor substrate, pad structures, dielectric structures, a second dielectric layer, and a void. The semiconductor substrate includes a first dielectric layer, the pad structures and the dielectric structure are disposed on the first dielectric layer, and each dielectric structure is disposed on a sidewall of one of the pad structures. A top surface of each dielectric structure is lower than a top surface of each pad structure in a vertical direction. The first dielectric layer includes a recess located between two adjacent dielectric structures in a horizontal direction. The second dielectric layer covers the pad structures, the dielectric structures, and the first dielectric layer. The void is located in the second dielectric layer. At least a part of the void is sandwiched between two adjacent pad structures in the horizontal direction, and the void is located directly above the recess in the vertical direction.