A chip package structure is provided. The chip package structure includes a substrate, a chip over the substrate, and a heat-spreading wall structure over the substrate and spaced apart from the chip. The chip package structure also includes a first heat conductive layer between the heat-spreading wall structure and the chip and a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The second heat conductive layer and the chip have different widths. The chip package structure further includes a heat-spreading lid extending across opposite edges of the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid includes a top plate and a lid sidewall structure, the top plate is over the lid sidewall structure, and a thickness of the lid sidewall structure continuously increases from the top plate toward the substrate.

Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embodiment, the V-groove is free from conductive material. In an embodiment, the electronic device further comprises an optical fiber inserted into the V-groove.

A semiconductor package includes a base chip, a first semiconductor chip group including a plurality of first semiconductor chips stacked on the base chip in a vertical direction, a second semiconductor chip group including a plurality of second semiconductor chips stacked on the first semiconductor chip group in the vertical direction, a plurality of first connection bumps on lower surfaces of the plurality of first semiconductor chips, a plurality of second connection bumps on lower surfaces of the plurality of second semiconductor chips, a first adhesive layer surrounding the plurality of first connection bumps and the first semiconductor chip group, and a second adhesive layer surrounding the plurality of second connection bumps and the second semiconductor chip group.

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

Aspects of the subject disclosure may include, for example, system, comprising a substrate having an interconnect in or on a surface of the substrate, a riser disposed over the surface, the riser being configured with one or more through riser vias for coupling to the interconnect, a device positioned over the surface, the device having one or more conductive contacts residing in a plane of the device, and one or more wire bonds coupling the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised toward or to the plane of the device such that at least one of the one or more wire bonds has a limited physical length. Other embodiments are disclosed.

A semiconductor package includes a first semiconductor chip having a first front surface and a first back surface opposing each other, and including first front connection pads, first back connection, and through-electrodes, a second semiconductor chip having a second front surface facing the first back surface and including second front connection pads, a substrate having a third back surface facing the first front surface and including upper pads and lower pads disposed opposite to each other, first bump structures between the first semiconductor chip and the second semiconductor, second bump structures between the first semiconductor chip and the substrate, and connection bumps. A first gap between the second front surface and the first back surface is equal to or greater than a second gap between the first front surface and the third back surface, and the second gap is greater than a thickness of the first semiconductor chip.

A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.

A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.