A semiconductor die includes a metalized layer on an upper surface of the semiconductor die and a plurality of metal wires having a defined shape. At least one end of each of the plurality of metal wires is bonded to the metalized layer and an upper portion of each of the plurality of metal wires may extend at least partially in parallel to the metalized layer of the semiconductor die. The plurality of metal wires are arranged in a sequence such that a channel is formed by a space between the metalized layer of the semiconductor die and the upper portion of each of the metal wires that may extend at least partially in parallel to the metalized layer. The upper portion of each of the plurality of metal wires is configured to be flush with an inner surface of a cover. A cooling system including such a semiconductor die is also provided.

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a panel-level chip packaging structure and method based on a steel plate platform. The packaging structure includes: a steel plate; a gold-nickel layer plated on the steel plate, where the gold-nickel layer is provided with upwardly protruding pins corresponding to a chip; the chip flipped to the corresponding pins; and a molded body coating the corresponding chip and the gold-nickel layer. According to the packaging structure and method of the present disclosure, an overall thickness of a chip-packaged product can be reduced. A wire bonding process and an electroplating process are further omitted, so that the overall thickness of chip packaging can be further reduced. An ultra-thin packaging structure can be implemented, the chip packaging efficiency can further be improved, and a complete-process chip packaging cycle can be shortened.

A semiconductor device comprising a terminal, a semiconductor element and a sealing resin. The semiconductor element is disposed on one side of the terminal in a first direction and electrically connected to the terminal. The sealing resin covers the semiconductor element and a part of the terminal. The sealing resin has a bottom surface disposed on an opposite side to the semiconductor element with respect to the terminal in the first direction. The terminal extends beyond the bottom surface.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

A current sensor integrated circuit (IC) package is flip-chip bonded using a conductive film to connect the IC circuit bond pads to the lead frame. A conductive film is positioned between the die surface of a semiconductor die and at least one signal lead of the lead frame. The conductive film is conductive in a first direction between the die and the signal lead and nonconductive in other directions. The conductive film is further configured to control a gap height between the die and the lead frame to reduce die tilt, thus improving the sensitivity and performance consistency of the package.

A semiconductor package including a first lead comprising a first surface and a second surface that is opposite to the first surface, at least one semiconductor chip that is placed on the first surface of the first lead, a connecting structure body that is connected to the first lead, and a molding layer configured to cover the first lead and the semiconductor chip. The first lead comprises a recess that is formed on the second surface of the lead, and the connecting structure body is placed in the recess. The semiconductor chip, the first lead, and the connecting structure body are electrically connected to each other.

A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

Compact inductors are disclosed herein. In certain embodiments, a compact inductor includes a ferrite core including a ferrite body, and a first conductive pillar and a second conductive pillar that each extend from a bottom surface of the ferrite body to a top surface of the ferrite body. Additionally, the compact inductor includes a planar substrate coupled to the top surface of the ferrite body. The planar substrate includes interconnect that electrically connects the first conductive pillar to the second conductive pillar.

In described examples, an integrated circuit (IC) package includes first and second external connectors at an external surface of the IC package, an IC die, and an antenna. The IC die is coupled to the first external connector. The antenna is coupled to the second external connector. The IC die and the antenna are not coupled within the IC package.

A semiconductor device includes an active layer having an active region, a source electrode and a drain electrode disposed on the active region of the active layer and extending along a first direction, a source metal layer disposed on the active region and electrically connected to the source electrode, a drain metal layer disposed on the active region and electrically connected to the drain electrode, and a source pad disposed on the active region. The source metal layer extends along a first direction and has a trapezoid shape in a plan view. The drain metal layer extends along the first direction and has a trapezoid shape in the plan view. The source pad is electrically connected to the source metal layer, and the source pad includes a body portion extending along a second direction and a branch portion extending along the first direction.