A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a protective element, and a sensor device. The protective element encapsulates the carrier. The sensor device is embedded in the carrier and the protective element. The sensor device includes a sensing portion and a protective portion adjacent to the sensing portion, and the protective portion of the sensor device has a first surface exposed from the protective element and the carrier.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

In some examples, a method for manufacturing a semiconductor package comprises coupling first and second semiconductor dies to a metal frame; covering the first and second semiconductor dies and the metal frame with a mold compound; coupling first and second passive components to the first and second semiconductor dies, the first and second passive components on an external surface of the mold compound; sawing through a portion of the metal frame from a first direction to form a first vertical surface of the metal frame, the first vertical surface having a first roughness due to the sawing; and laser cutting through the mold compound and a remainder of the metal frame from a second direction opposing the first direction to form a second vertical surface on the metal frame and a third vertical surface on the mold compound, the second vertical surface having a second roughness due to the laser cutting and the third vertical surface having a third roughness due to the laser cutting.

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

An electronic device includes a substrate, a base substrate, a metal connection body, a support body, a metal body, and a via. The substrate includes one main surface with a functional element and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that the one main surface faces the base substrate. The metal body is in contact with the support body and includes at least a portion extending to outside the substrate in plan view from the support body. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.

The device may include a core. The device may include built-up layers arranged over the core. The device may also include a ground path disposed in a first built-up layer of the built-up layers. The device may also include a power path disposed in a second built-up layer of the built-up layers. The device may also include a multi-terminal capacitor on a top layer of the built-up layers. The multi-terminal capacitor may be coupled to the ground path and the power path through respective vias passing through the built-up layers. The respective vias may be arranged to alternate such that respective vias coupled to the power path neighbor a respective via coupled to the ground path.

A power device and method of making said power device. The device including a gate controller coupled to a first substrate. A first set of one or more transistor devices is coupled to a second substrate and a second set of one or more transistor devices is also coupled to the second substrate. The first set of transistor devices and second set of transistor devices are communicatively coupled to the gate controller.

A semiconductor package includes a plurality of leads, each lead having a planar portion and a non-planar portion, in which: the planar portion has a first side and a second side opposing the first side, and the non-planar portion is at an angle with the planar portion. The semiconductor package includes a first device mechanically coupled to the first side of the planar portion with first interconnects and a second device mechanically coupled to the second side of the planar portion with second interconnects. The semiconductor package includes mold compound covering the first device and the second device, in which: a first mold overlay is on a side of the first device distant from the leads, and a second mold overlay is on a side of the second device distant from to the leads.

A package structure includes a redistribution layer, a plurality of semiconductor dies and a bonding layer. The redistribution layer has a first surface and a second surface opposite to the first surface, and includes a plurality of conductive lines and a plurality of conductive vias connected to the plurality of conductive lines. Seed layers are located below the conductive lines and the conductive vias, wherein a portion of the seed layers is revealed at the second surface. The semiconductor dies are disposed on the first surface of the redistribution layer and electrically connected to the redistribution layer. The bonding layer is disposed on the second surface of the redistribution layer, wherein the bonding layer comprises a plurality of bonding pads, and a bottom surface of the plurality of bonding pads is joined to the portion of the seed layers revealed at the second surface.