Patent classifications
H10P14/6536
Selective etching of silicon nitride dielectrics with MICROWAVE oxidation
According to one or more embodiments, a method includes positioning a substrate within a processing chamber. The substrate includes a hardmask layer disposed over a surface of the substrate, a first layer disposed over the hardmask layer, and a second layer disposed over the first layer. The method further includes flowing a process gas into the processing chamber, and delivering a microwave energy for a period of time to the process gas to selectively etch the hardmask layer and the first layer, wherein delivering the microwave energy to the process gas does not generate a plasma.
Large area gapfill using volumetric expansion
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.
SEMICONDUCTOR DEVICES WITH ASYMMETRIC INSULATING LAYERS AND METHODS OF FABRICATION THEREOF
Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region disposed in the semiconductor layer, a drain region disposed in the semiconductor layer, a gate electrode, and an insulating layer disposed between a portion of the gate electrode and the semiconductor layer. The insulating layer has a first sidewall extending toward the source region and a second sidewall extending toward the drain region, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.
Methods for bonding semiconductor elements
Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.
SUBSTRATE CHUCKING WITH MULTISCALE WAFER STRESS MODULATION
Disclosed systems and techniques are directed to improving chucking of substrates using stress-compensation beams with multiscale irradiation doses. The techniques include decomposing a profile of a deformation of a substrate into a plurality of harmonics, and identifying, using chuckability reference data, one or more harmonics of the plurality of harmonics having an amplitude above a maximum amplitude capable of being flattened by a predetermined clamping pressure exerted on the substrate by a chuck. The techniques further include determining, based at least on a subset of the one or more harmonics, settings of a stress-modulation beam, forming a stress-compensation layer (SCL) on the substrate causing a modification of the deformation of the substrate, and irradiating the SCL with the stress-modulation beam, wherein the stress-modulation beam causes a reduction of the deformation of the substrate.