Approaches of the disclosure relate to methods for forming self-aligned backside contacts in a semiconductor device. One method may include forming a trench in a stack of layers, wherein the stack of layers comprises a plurality of alternating first layers and second layers atop a base layer, and wherein the trench is defined by a set of sidewalls and a bottom extending between the set of sidewalls. The method may further include implanting the bottom of the trench to form an etch stop layer within the base layer, forming a recess in the base layer by removing the base layer selective to the etch stop layer, and filling the recess with a temporary material. The method may further include depositing a source/drain material within the trench, wherein the source/drain material is formed over the temporary material.

Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.

In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

A device includes a source region and a drain region over a substrate. The device further includes a gate structure at least partially between the source region and the drain region, and a gate contact over the gate structure. The gate contact has an upper portion and a lower portion below the upper portion. The lower portion is more tapered than the upper portion.

A method of processing a substrate that includes: selectively depositing a self-assembled monolayer (SAM) on a metal line of the substrate, the SAM being in contact with the metal line, a surface of the substrate further including a first dielectric material that surrounds the metal line; selectively depositing a second dielectric material over the first dielectric material; forming a dielectric layer by depositing a third dielectric material over the second dielectric material and the SAM; and patterning the dielectric layer.

A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.