A method for producing a vertical nitride semiconductor device includes: preparing a semiconductor substrate containing a Group III nitride semiconductor and having a donor element concentration of 110.sup.19 cm.sup.3 or more; and forming a support layer containing a metal and having a thickness of 10 m or more on a first main surface of the semiconductor substrate.

A semiconductor device includes a substrate, a dielectric layer on the substrate, a first epitaxial layer on the dielectric layer, and a second epitaxial layer on the first epitaxial layer.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which Ge concentration in the substrate is 310.sup.18 cm.sup.3 or more; and among peaks appearing in a histogram of diameters of etch pits during etching applied to the main surface with an alkaline etching solution, a first peak having a smallest diameter is a single peak having no shoulder.

A Group-III element nitride substrate includes a first main surface and a second main surface facing each other, wherein, in the first main surface, crystallinity of a first part positioned on a central portion thereof is higher than crystallinity of a second part positioned outside the first part.

A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

An object of the present invention is to provide a GaN crystal long in light emission lifetime by time-resolved photoluminescence measurement and provide high-quality GaN crystal and GaN substrate that have few specified crystal defects affecting the light emission lifetime. A gallium nitride crystal having a light emission lifetime by time-resolved photoluminescence measurement, of 5 ps or more and 200 ps or less, and satisfying at least one of the following requirement (i) and requirement (ii): (i) an FWHM in a 004 diffraction X-ray rocking curve is 50 arcsec or less at least one position of the crystal; and (ii) a dislocation density is 510.sup.6 cm.sup.2 or less.