Described are semiconductor devices, e.g., PMOS and/or NMOS, with improved stress in the channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel extending between the source region and the drain region, and a diffusion break patterned through the device. The self-aligned diffusion break opening is gap filled a stressed dielectric material using a densified seam-free silicon-containing material gap fill process.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

A semiconductor device includes: a drift region of a first conductivity type between first and second surfaces of a semiconductor body; a first region of a second conductivity type at the second surface; and a field stop region of the first conductivity type between the drift region and first region. The field stop region includes first and second sub-regions with hydrogen related donors. A p-n junction separates the first region and first sub-region. A concentration of hydrogen related donors, along a first vertical extent of the first sub-region, steadily increases from the pn-junction to a maximum value, and steadily decreases from the maximum value to a value at a first transition between the sub-regions. A second vertical extent of the second sub-region ends at a second transition to the drift region where the concentration of hydrogen related donors equals 10% of the value at the first transition.

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

A silicon carbide wafer, including: a semiconductor substrate containing silicon carbide and having a first surface and a second surface opposite to each other; an epitaxial layer provided at the first surface of the semiconductor substrate and having a dopant concentration lower than that a dopant concentration of the semiconductor substrate; and a crystal defect introduced region provided in the semiconductor substrate, at a predetermined depth from the first surface of the semiconductor substrate, the crystal defect introduced region being in contact with the epitaxial layer and containing a number of point defects that are atomic vacancies created by irradiation of an electron beam on the semiconductor substrate.

Provided is a semiconductor device including a MOS gate structure provided in a semiconductor substrate, including: an interlayer dielectric film which includes a contact hole and is provided above the semiconductor substrate; a conductive first barrier metal layer provided on side walls of the interlayer dielectric film in the contact hole; a conductive second barrier metal layer stacked on the first barrier metal layer in the contact hole; and a silicide layer provided on an upper surface of the semiconductor substrate below the contact hole, in which the first barrier metal layer is more dense than the second barrier metal layer, and a film thickness thereof is 1 nm or more and 10 nm or less.

A semiconductor memory device includes a substrate, a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern extending in a first horizontal direction above the substrate, and spaced apart from each other, the first semiconductor pattern comprising a channel region, a source region, and a drain region, the channel region, source region, and drain region arranged in the first horizontal direction with the channel region therebetween, a first word line and a second word line, the first word line and the second word line extending in the second horizontal direction above the first semiconductor pattern, and spaced apart from each other in the vertical direction, a bit line connected to the source region of the first semiconductor pattern, and the bit line extending in the vertical direction, and a cell capacitor connected to the drain region of the first semiconductor pattern.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 m or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 m or more in a direction from the local maximum of the hydrogen peak toward the upper surface.

Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.