An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillars that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillars are conductive wires. A package body encapsulates the electronic component and the conductive pillars. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive pillars. In one embodiment, the electrical connection is made through the package body. In another embodiment, the electrical connection is made through the substrate.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y11 mass %, x+14y42 mass %, and x5.1 mass %.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A temporary fixing composition contains an organic component in a proportion of 42 mass % or more and 95 mass % or less. The organic component is solid at 25 C. and has a 95% mass loss temperature in nitrogen of 300 C. or lower. The temporary fixing composition is used to temporarily fix a first bonding target material and a second bonding target material to each other before the two bonding target materials are bonded to each other. A method for producing a bonded structure of the present invention includes temporarily fixing a first bonding target material and a second bonding target material to each other with the temporary fixing composition disposed therebetween and firing the temporarily fixed two bonding target materials to bond the two bonding target materials to each other.

A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.

Provided is a thermosetting resin composition containing: (A) silver particles including secondary particles having an average particle size from 0.5 to 5.0 m, the secondary particles being formed by aggregation of primary particles having an average particle size from 10 to 100 nm; and (B) a thermosetting resin.

A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface. The first redistribution structure includes a first pad and a second pad, the first pad is adjacent to the first surface, and the second pad is adjacent to and exposed from the second surface. The chip package structure includes a chip package bonded to the first pad through a first bump, wherein a first width of the first pad decreases in a first direction away from the chip package, and a second width of the second pad decreases in the first direction. The chip package structure includes a second bump over the second pad.