Patent classifications
H10W72/325
Paste composition and semiconductor device
This paste composition includes silver particles (A), a thermosetting resin (B), a curing agent (C), and a solvent (D). A shrinkage rate after curing of the paste composition is 15% or less.
WAFER BONDING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURED USING THE SAME
A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.
SEMICONDUCTOR STRUCTURES AND METHODS FOR MANUFACTURING THE SAME
A semiconductor device includes a dielectric layer disposed over a substrate and having a top surface; a top metal layer disposed within a portion of the dielectric layer and extending to the top surface of the dielectric layer; a first passivation layer disposed over the top surface of the dielectric layer; a redistribution layer (RDL) disposed over the first passivation layer, the RDL including an un-etched portion having a first thickness; and a second passivation layer disposed over the RDL, the second passivation layer having a second thickness over the un-etched portion of the RDL that is 40% or more of the first thickness.
IMAGE SENSOR PACKAGING STRUCTURES AND RELATED METHODS
Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.
INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME
A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.
Thermosetting resin composition, semiconductor device and electrical/electronic component
There are provided a thermosetting resin composition for semiconductor bonding and a thermosetting resin composition for light emitting device which have high thermal conductivity and an excellent heat dissipation property and are capable of reliable pressure-free bonding of a semiconductor element and a light emitting element to a substrate. A thermosetting resin composition comprising: (A) silver fine particles ranging from 1 nm to 200 nm in thickness or in minor axis; (B) a silver powder having an average particle size of more than 0.2 m and 30 m or less; (C) resin particles; and (D) a thermosetting resin, wherein an amount of the resin particles (C) is 0.01 to 1 part by mass and an amount of the thermosetting resin (D) is 1 to 20 parts by mass, to 100 parts by mass being a total amount of the silver fine particles (A) and the silver powder (B).
Semiconductor device and semiconductor package
A semiconductor device includes a plurality of semiconductor chips sequentially stacked on a substrate, an underfill layer between the plurality of semiconductor chips and between the substrate and a lowermost one of the plurality of semiconductor chips, and a molding resin extending around the plurality of semiconductor chips. The molding resin extends to a space between an uppermost one of the plurality of semiconductor chips and a semiconductor chip sequentially beneath the uppermost one of the plurality of semiconductor chips.
SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING
The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
SEMICONDUCTOR PACKAGE
A semiconductor package including a substrate, a chip stack stacked on a top surface of the substrate, and a mold layer provided on the top surface of the substrate and the chip stack is provided. The chip stack include a first chip having a first region provided with chip pads and second regions provided at a first side and a second side of the first region. The chip pads of the first chip may be bonded to substrate pads of the substrate to form a single object. Each of the second regions of the first chip may be spaced apart from the top surface of the substrate in a direction perpendicular to the top surface of the substrate. The mold layer may fill a space between each of the second regions and the top surface of the substrate.
Anisotropic conductive film and display device including same
The disclosure relates to a display device and an anisotropic conductive film. An anisotropic conductive film disposed between a display panel and a printed circuit board, the anisotropic conductive film including a base resin, a plurality of first conductive balls dispersed in the base resin, each of the plurality of first conductive balls including a core made of a polymer material and at least one metal layer surrounding the core, and a plurality of second conductive balls dispersed in the base resin, each of the plurality of second conductive balls being made of a meltable material, and the anisotropic conductive film having a first area in which the anisotropic conductive film overlaps the first pad electrode and the first lead electrode in a thickness direction of the display device, and a second area as an area disposed between the first lead electrode and the second lead electrode. Each of the metal layer of the first conductive ball and a surface of the second conductive ball are in contact with both the first pad electrode and the first lead electrode.