A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A semiconductor module, including a semiconductor chip, a sealed main body portion sealing the semiconductor chip and having a pair of attachment holes penetrating therethrough, a heat dissipation plate in contact with the sealed main body portion. The heat dissipation plate is positioned between the attachment holes in a plan view of the semiconductor module. The semiconductor module further includes a pair of rear surface supporting portions and/or a pair of front surface supporting portions protruding respectively from rear and front surfaces of the sealed main body portion. In the plan view, the heat dissipation plate is formed between the pair of attachment holes, which are in turn between the pair of rear surface supporting portions. The pair of front surface supporting portions are formed substantially between the pair of attachment holes in the plan view.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

A semiconductor package includes a redistribution structure including a first redistribution layer, a semiconductor chip on the redistribution structure and having a contact pad electrically connected to the first redistribution layer, a vertical connection conductor on the redistribution structure and electrically connected to the first redistribution layer, a molding portion disposed on the redistribution structure, a second redistribution layer disposed on the molding portion, connected to the vertical connection conductor, and having a plurality of first pads, each of the plurality of first pads having an alignment hole, a plurality of second pads respectively disposed on the plurality of first pads and having a side portion covering an inner sidewall of the alignment hole, the alignment hole having an inner space surrounded by the side portion, and a protective insulating layer covering the second redistribution layer, and having a plurality of contact openings respectively exposing the plurality of second pads.