A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.

Example embodiments are directed to a semiconductor device including a substrate, a substrate pad placed on the substrate, a substrate insulation layer configured to surround at least a portion of the substrate pad, a passivation layer placed on the substrate insulation layer and a bump pad placed on the passivation layer, electrically connected to the substrate pad and including solder bumps. The bump pad includes a connector recessed toward the substrate, and the connector, when viewed in a first direction perpendicular to a surface of the substrate, includes a shape, in order to reduce or lower a defect occurring in solder bumps when a degree of expansion and contraction varies due to differences in the coefficient of thermal expansion (CTE).

According to some embodiments, a semiconductor package includes a base chip, a plurality of memory chips on the base chip, and a bonding metal. The plurality of memory chips includes a first memory chip disposed lowermost among the plurality of memory chips. The bonding metal is disposed on a first outer portion of a top surface of the base chip and a second outer portion of a bottom surface of the first memory chip. The bonding metal is formed by coupling a first metal pattern disposed on the first outer portion to a second metal pattern disposed on the second outer portion.

A substrate assembly and an electronic device are provided. The substrate assembly includes a substrate, a first metal layer, a second metal layer, a first conductive layer, and an insulating layer. The first metal layer is disposed on the substrate. The second metal layer is disposed on the substrate. The first conductive layer is disposed between the first metal layer and the second metal layer, wherein the first conductive layer overlaps with a part of the first metal layer and overlaps a part of the second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer and has an opening through which the part of the first metal layer and the second metal layer are electrically connected with each other.

Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.

A semiconductor structure includes a first conductive element having a first side, a second conductive element having a second side contacting the first side of the first conductive element; and a blocking member, surrounded by the first conductive element and adjacent to the second conductive element. A first width of the first side is substantially greater than a second width of the second side, and at least a portion of the first conductive element is disposed between the second conductive element and the blocking member. A method of manufacturing a semiconductor structure, includes providing a dielectric; patterning the dielectric to form a first opening having a first portion and a second portion connected to the first portion, wherein a blocking member is disposed within the first portion; disposing a first conductive element and a second conductive element into the first portion and the second portion of the first opening respectively.

A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

An integrated device provides a measure of a quantity dependent on current through an electrical conductor, having: a sensing and processing sub-system: an electrical conductor conducting current: an insulating material encapsulates the sensing and processing sub-system and maintains the electrical conductor in a fixed and spaced relationship to the sensing and processing sub-system. The insulating material insulates the electrical conductor from the sensing and processing sub-system. Sensing and processing sub-system sensing circuitry includes magnetic field sensing elements adjacent the electrical conductor. The sensing circuitry provides a measure of the quantity as a weighted sum and/or difference of magnetic field sensing elements outputs caused by current through the electrical conductor adjacent the magnetic field sensing elements. A voltage sensing input senses a measure of voltage associated with the current conductor. Sensing and processing sub-system output circuitry provides an output measure of the quantity from the sensed measure of current and voltage.