Patent classifications
H10W72/932
Backlight unit and display device including the same
A backlight unit and a display device including the same are disclosed. More specifically, a backlight unit is disclosed that includes a plurality of light sources disposed on a glass substrate and disposed in a plurality of rows and a plurality of columns, and first and second transistors disposed on the glass substrate and spaced apart from each other, wherein each of the first transistor and the second transistor is disposed so as not to overlap the plurality of light sources disposed at points where two rows and two columns cross each other. Thus, image quality is excellent.
Light-emitting device
A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer and a second semiconductor layer, wherein in a top view, the semiconductor stack comprises an outer peripheral region and an inner region, the outer peripheral region exposes the first semiconductor layer, and the second semiconductor layer is disposed in the inner region; an outer insulated structure comprising an insulation layer and a protective layer, the insulation layer comprising a plurality of first insulation layer outer openings and a second insulation layer opening; a first electrode covering the plurality of first insulation layer outer openings; and a second electrode covering the second insulation layer opening, wherein the outer insulated structure comprises a total thickness gradually decreasing from the outer peripheral region to the inner region.
Semiconductor chip and semiconductor package
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.
Driving substrate, micro LED transfer device and micro LED transfer method
A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.
SEMICONDUCTOR PACKAGE
Provided is a semiconductor package. The semiconductor package may include: a first semiconductor chip having a device region and a dummy region surrounding the device region in a planar view, second semiconductor chips on an upper surface of the device region of the first semiconductor chip, and a molding layer covering the second semiconductor chips on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor substrate, a first lower pad arranged on a lower surface of the first semiconductor substrate, a first upper insulating layer including a first insulating layer and a second insulating layer and being arranged on an upper portion of the first semiconductor substrate, and a first upper pad and a trench region, which are arranged within the second insulating layer.
Lead frame, packaging structure and packaging method
A lead frame includes a base comprising a bearing surface for bearing a chip. The bearing surface includes a soldering region, with a solder layer arranged in the soldering region. The solder layer is configured for fixing the chip on the bearing surface. The lead frame includes a groove provided on the bearing surface in a thickness direction of the base. The groove is located outside the soldering region and surrounds at least part of the soldering region along the outer periphery of the soldering region for receiving solder paste overflowed from the soldering region. A depth of the groove is based on a thickness of the base. A packaging structure including the lead frame and a packaging method using the lead frame are also provided.
SEMICONDUCTOR DEVICE
ABSTRACT OF DISCLOSURE A semiconductor device includes a dielectric layer, a metal wire, and a plurality of via structures. The dielectric layer is disposed on a substrate, and the metal wire is disposed within the dielectric layer. The via structures are separately disposed within the dielectric layer, on the metal wire and physically contacting the metal wire. The via structures are arranged along a first direction and a second direction being perpendicular to the first direction, at least into a 22 array, wherein a ratio between a total area of the via structures and an area of the metal wire is greater than 0.13.
Anisotropic conductive film and display device including same
The disclosure relates to a display device and an anisotropic conductive film. An anisotropic conductive film disposed between a display panel and a printed circuit board, the anisotropic conductive film including a base resin, a plurality of first conductive balls dispersed in the base resin, each of the plurality of first conductive balls including a core made of a polymer material and at least one metal layer surrounding the core, and a plurality of second conductive balls dispersed in the base resin, each of the plurality of second conductive balls being made of a meltable material, and the anisotropic conductive film having a first area in which the anisotropic conductive film overlaps the first pad electrode and the first lead electrode in a thickness direction of the display device, and a second area as an area disposed between the first lead electrode and the second lead electrode. Each of the metal layer of the first conductive ball and a surface of the second conductive ball are in contact with both the first pad electrode and the first lead electrode.
Method for preparing display substrate and display substrate
Disclosed is a method for preparing a display substrate, including: providing a driving substrate; wherein the driving substrate includes: a base substrate; a pixel driving circuit layer; a first pad and a second pad, spaced from each other, and connected to the pixel driving circuit layer; and an electrostatic protection alignment, spaced from the first pad; and transferring a light-emitting element to the driving substrate, such that an anode of the light-emitting element is connected in alignment with the first pad and a cathode of the light emitting-element is connected in alignment with the second pad. The first pad includes a first toothed tip arranged on a side of the first pad facing the electrostatic protection alignment, and the electrostatic protection alignment includes a second toothed tip arranged on a side of the electrostatic protection alignment facing the first pad.
CONTACT STRUCTURE WITH FLEXIBLE DIELECTRIC BARRIER
A contact structure and a method of forming the contact structure. The contact structure includes: a metallic contact; a flexible dielectric material; and an interlevel dielectric material surrounding, and in direct contact with, both the metallic contact and the flexible dielectric material. The flexible dielectric material has a lower modulus of elasticity than does the interlevel dielectric material. The flexible dielectric material and the interlevel dielectric material are different dielectric materials. The flexible dielectric material may be positioned to be compressed in response to a shearing force generated at an interface between the flexible dielectric material and the metallic contact during expansion of the metallic contact. The metallic contact may include a bottom portion and a top portion, wherein the top portion includes an upper part and a lower part, and wherein the flexible dielectric material is in direct contact with the lower part of the top portion.