A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.

The invention relates to a sintering paste consisting of: (A) 30 to 40 wt. % of silver flakes with an average particle size ranging from 1 to 20 m, (B) 8 to 20 wt. % of silver particles with an average particle size ranging from 20 to 100 nm, (C) 30 to 45 wt. % of silver(I) oxide particles, (D) 12 to 20 wt. % of at least one organic solvent, (E) 0 to 1 wt. % of at least one polymer binder, and (F) 0 to 0.5 wt. % of at least one additive differing from constituents (A) to (E).

A semiconductor package structure includes a first package component, a second package component disposed over the first package component, a plurality of connectors between the first package component and the second package component, an underfill between the first package component and the second package component and surrounding the plurality of connectors, and a plurality of heat sink fibers in the underfill. A thermal conductivity of the plurality of heat sink fibers is greater than a thermal conductivity of the underfill.

In a general aspect, a method of sintering a semiconductor device assembly having a surface projection includes applying sintering material to a die attach surface. The method also includes disposing a semiconductor die on the sintering material, the semiconductor die having a surface including a substantially planar portion and at least one projection extending from the substantially planar portion in a direction orthogonal to the surface. The method also includes disposing a film on the surface of the semiconductor die, the film including at least one spacer, where the film is disposed such that the at least one spacer contacts the substantially planar portion. The method also includes applying pressure to the film. The method also includes applying thermal energy at a first sintering temperature to sinter the semiconductor die to the die attach surface. The method also includes removing the film.

In examples, a semiconductor package comprises a semiconductor die having a device side including circuitry and a non-device side opposing the device side. The semiconductor package comprises a polyimide substrate coupled to the non-device side of the semiconductor die by an adhesive layer. The semiconductor package comprises a conductive terminal coupled to the polyimide substrate by the adhesive layer, and a bond wire coupled to the device side of the semiconductor die and to the conductive terminal. The semiconductor package comprises a mold compound covering the semiconductor die, the polyimide substrate, the bond wire, and at least part of the conductive terminal, with the conductive terminal extending to an exterior of the mold compound.

A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Integrated circuit (IC) structures and electronic packages that utilized an inorganic-convertible polymer to improve bond strength and thermal conductivity are described. In one embodiment, the inorganic-convertible polymer acts as a side fill material to seal a die periphery and improve direct bonding strength. In another embodiment, the inorganic-convertible polymer acts as a thermal bonding layer to increase the thermal conductivity between a die and a thermal solution.