A double-sided cooling package for a double-sided, bi-directional junction transistor can include a double-sided, bi-directional, junction transistor chip with an individual, double-sided, bi-directional power switch (collectively, a DSTA). The DSTA can be sandwiched between heat sinks. Each heat sink can include a direct plating copper (DPC) structure, a direct copper bonding (DCB) structure or a direct aluminum bond (DAB) structure. In addition, each heat sink can have opposed first and second copper layers on a substrate, and copper contacts that extend from a respective second copper layer through vias in each substrate to an exterior of the cooling package.

A method of applying a sinterable film to a substrate during a surface mount technology (SMT) process comprises: providing a substrate; providing a preform comprising a support film, the support film having a first surface and a second surface opposite the first surface, the support film being laminated with a sinterable film of metal particles (e.g., Ag, Ag alloy, Au, Au alloy, Cu, Cu alloy, Rd, Rd alloy, Ni, Ni alloy, Al, Al alloy, Ag-coated Cu, Cu-coated Ag) on the first surface but not on the second surface; providing a pick-and-place machine comprising a placement head; picking up the preform via the second surface using the placement head of the pick-and-place machine; placing the preform in contact with the substrate using the pick-and-place machine, wherein the contact is via the sinterable film; attaching the sinterable film to the substrate; and separating the support film from the sinterable film. The placement head may comprise a vacuum nozzle, wherein picking up the preform via the support film comprises applying a vacuum to the second surface using the vacuum nozzle. Separating the support film from the sinterable film may be carried out by moving the placement head of the pick-and-place machine away from the support film while maintaining the vacuum. The support film may be discarded from the pick-and-place machine by removing the vacuum. The support film may be used to manufacture a further preform.

A device includes: a first substrate; a second substrate; interconnects bonding the first substrate to the second substrate; and a polymer brush-based underfill layer in a gap between the first substrate and the second substrate. A method includes: attaching initiator molecules to one or more surfaces in a gap between a first substrate and a second substrate of a bonded structure, where the first substrate and the second substrate are bonded by interconnects; growing polymer chains from the initiator molecules; and annealing the bonded structure to form an underfill layer from the polymer chains in the gap.

A chip packaging structure includes a busbar with a plurality of chip slots; a plurality of chip units respectively embedded into the plurality of chip slots, and including at least two different types of chip units, with electrochemical plating arranged at a bottom of the chip slot, and the chip unit includes a conductive layer, a chip main body, and a DTS layer sequentially stacked on the plating; and a channel arranged on the busbar and located between adjacent chip slots. By integrating and embedding the different types of chip units into the same busbar, subsequent manufacturing of a circuit board is facilitated. Additionally, the channel absorbs busbar thermal expansion caused by heat generated during operation of the chip units, and reduces thermal coupling between the chip units, thereby preventing the chip units from interfering with each other, and ensuring firm positions and stable performance of the chip units.

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: an upper phase multi-chip module including: a low-voltage upper phase controller; a high-voltage upper phase A controller; an upper phase A galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase A controller; a high-voltage upper phase B controller; an upper phase B galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase B controller; a high-voltage upper phase C controller; and an upper phase C galvanic isolator connecting the low-voltage upper phase controller to the high-voltage upper phase C controller.

A method includes forming a first tacking layer on a first connection partner, arranging a first layer on the first tacking layer, forming a second tacking layer on the first layer, arranging a second connection partner on the second tacking layer, heating the tacking layers and first layer, and pressing the first connection partner towards the second connection partner, with the first layer arranged between the connection partners, such that a permanent mechanical connection is formed between the connection partners. Either the tacking layers each include a second material evenly distributed within a first material, the second material being configured to act as or to release a reducing agent, or the tacking layers each include a mixture of at least a third material and a fourth material, the materials in the mixture chemically reacting with each other under the influence of heat such that a reducing agent is formed.

A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.

A package includes an at least partially electrically conductive front-side connection body and an electronic component having an epitaxial layer and being assembled with the front-side connection body. A distance between the epitaxial layer and the front-side connection body is less than 50 m. A method of manufacturing the package is also described.

Aspects of the subject disclosure may include, for example, bonding III-Nitride epitaxial layer(s) to a carrier wafer, wherein the III-Nitride epitaxial layer(s) are grown on a non-native substrate, after the bonding, removing at least a portion of the non-native substrate from the III-Nitride epitaxial layer(s), processing the III-Nitride epitaxial layer(s) to derive an array of III-Nitride islands, establishing a metal layer over the array of III-Nitride islands, resulting in an array of metal-coated III-Nitride islands, arranging the carrier wafer relative to a host wafer to position the array of metal-coated III-Nitride islands on a surface of the host wafer, causing the array of metal-coated III-Nitride islands and the surface of the host wafer to eutectically bond, and removing the carrier wafer to yield an integrated arrangement of III-Nitride islands on the host wafer. Additional embodiments are disclosed.

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a first power module, the first power module including: a first substrate including a first conductive layer; a second substrate including a second conductive layer; a power switch between the first conductive layer and the second conductive layer, the power switch including a gate connection, wherein the power switch is configured to selectively electrically connect the first conductive layer to the second conductive layer based on a signal to the gate connection; and a point-of-use controller between the first conductive layer and the second conductive layer, the point-of-use controller configured to provide the signal to the gate connection to control the power switch.