Disclosed is an integrated circuit device. In some aspects, a device includes a first wafer including a first dielectric layer, a first set of bonding pads disposed in the first dielectric layer and a first circuit disposed on the first dielectric layer, and a second wafer including a second dielectric layer, a second set of bonding pads disposed in the second dielectric layer and a second circuit disposed on the second dielectric layer. The device further includes through-vias including at least one power via in the second wafer, and a backside power distribution network (BSPDN) layer disposed on the second wafer. The first set of bonding pads is bonded with the second set of bonding pads.

Various embodiments of the present technology may provide a method for fabricating a semiconductor structure. The method may include receiving a source substrate having a dielectric layer and a conductive feature, selectively depositing a barrier layer only on a top surface of the conductive feature, modifying a top surface of the dielectric layer, and removing the barrier layer after modifying the dielectric layer. The method may also include cleaning a top layer of the dielectric and conductive feature prior to depositing the barrier layer.

A semiconductor device assembly includes a plurality of stacks of semiconductor devices, each including multiple devices operably coupled by TSVs to external package contacts through an RDL, and a device connection layer formed over the plurality of stacks and including a first plurality of contacts coupled to the TSVs, a second plurality of contacts facing away from the TSVs, a first plurality of conductors operably coupling contacts of the first plurality to corresponding contacts of the second plurality, and a second plurality of conductors operably coupling contacts of the second plurality to other contacts of the second plurality. The assembly further includes a multi-reticle semiconductor device disposed over the device connection layer and including a continuous semiconductor substrate having a plurality of circuit regions separated by a reticle-edge region absent any electrical conductors. The second plurality of conductors in the device connection layer operably interconnect the plurality of circuit regions.

A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.

A bonded structure is provided. The bonded structure includes a first stack structure on a substrate, a second stack structure over the first stack structure, and a bonding interface between the first stack structure and the second stack structure. The second stack includes a via structure extending in the second stack structure and towards the bonding interface, the via structure having a first width closer to the bonding interface and a second width further away from the bonding interface. The first width is greater than the second width.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.

Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.

A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.

A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through hybrid bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.