Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.

A device comprising a memory device comprising a first memory chip comprising a first memory portion; and a first processor in memory portion, wherein the first processor in memory portion includes a first plurality of logic cells and at least one first capacitor; and a second memory chip coupled to the first memory chip.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, a second semiconductor die, a bridge structure and a memory structure. The substrate includes a wiring structure disposed in dielectric layers. The first semiconductor die and the second semiconductor die are disposed over the substrate. The bridge structure is embedded in the substrate. The first semiconductor die is electrically coupled to the second semiconductor die through the bridge structure. Moreover, the memory structure is embedded in the substrate and is positioned below the bridge structure.

In an aspect there is provided a 3D IC device comprising: a package wiring plane comprising a global VDD voltage node and a global VSS voltage node; a die stack arranged over the package wiring plane and comprising a number of stacked dies stacked on top of each other; a metal interconnect layer arranged on top of a top stacked die of the die stack; and a pass-through interconnect extending vertically through each stacked die of the die stack and connecting the metal interconnect layer to the global VDD voltage node; wherein each stacked die of the die stack has a bottom side and a top side, a local VDD voltage contact on its top side and a local VSS voltage contact on its bottom side.

A carrier assembly for semiconductor device may include a first carrier attached to a front surface of a base wafer, the first carrier including a first stiffness reinforcement structure having a first surface facing the base wafer and a second surface opposite to the first surface and including a first adhesive member disposed between the first surface of the first reinforcement structure and the front surface of the base wafer; and a second carrier attached to the second surface of the first stiffness reinforcement structure, the second carrier including a second stiffness reinforcement structure having a first surface facing the base wafer and a second surface opposite to the first surface of the second stiffness reinforcement structure and including a second adhesive member disposed between the first stiffness reinforcement structure and the second stiffness reinforcement structure.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.

Microelectronic integrated circuit package structures include a package structure comprising a first die on a first dielectric material and a second die on second dielectric material, where the first die is adjacent to the second die. A third die is below the first die and is hybrid bonded to the first die. a fourth die is below the second die, and is hybrid bonded to the second die. A layer comprising nitrogen and silicon is directly on top surfaces of the first die and the second die. A fill dielectric material is between the first die and the second die, and a lid over the fill dielectric material.

According to one aspect of the present disclosure, a semiconductor package structure is provided. The semiconductor package structure may include a first semiconductor chip and a second semiconductor chip stacked along a first direction and coupled with each other. The first semiconductor chip may include a first die and a second die that are bonded along the first direction. The first die may be coupled with the second die through a first bonding contact. The semiconductor package may include a first connection structure extending through the first die along the first direction. The semiconductor package structure may include a second connection structure extending through the second die along the first direction. The first bonding contact is located between the first connection structure and the second connection structure in the first direction. The first connection structure may be coupled with the second connection structure through the first bonding contact.