A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes an inductor, and inductor includes a plurality of semiconductor builds bonded together with one on top of another, each of the plurality of semiconductor builds having two or more through-silicon vias (TSVs) that are vertically aligned with two or more TSVs of an adjacent one of the plurality of semiconductor builds; and a plurality of horizontal bars conductively connecting two of the two or more TSVs of each of the plurality of semiconductor builds, where the two or more TSVs of each of the plurality of semiconductor builds and the plurality of horizontal bars are concatenated together to have a spiral shape, in a vertical plane, that spans across the plurality of semiconductor builds. A method of manufacturing the semiconductor structure is also provided.

The semiconductor package includes a semiconductor chip; a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on the semiconductor chip along a vertical direction; first inner bonding pads accommodated in the first inner bonding layer on the bonding region of the substrate, and first inner align key patterns accommodated in the first inner bonding layer on the align key region of the substrate; first outer bonding pads accommodated in the first outer bonding layer on the bonding region of the substrate and first outer align key patterns accommodated in the first outer bonding layer on the bonding region of the substrate; a second bonding layer including a second outer bonding layer and a second inner bonding layer sequentially stacked on the first bonding layer along the vertical direction; and a second semiconductor chip disposed on the second bonding layer.

System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and an improved-thermal high-bandwidth memory (HBM) device each integrated with the base substrate. The improved-thermal HBM device can include an interface die and a stack of one or more memory dies carried by the interface die. The interface die includes an input/output (IO) circuit, which is communicably coupled via one or more IO circuit interfaces to the host device through communication channels of the base substrate. The IO circuit interfaces of the improved-thermal HBM device distributes physical interconnect bumps for transmit data and receive data in a dispersed manner along an edge of the interface die in a manner to reduce the occurrence of thermal hotspots.

A device package includes a first tier, a second tier stacked upon the first tier, and a through tier via unitarily penetrating through the first and second tiers. The first tier includes a first device and a first interconnect structure electrically coupled to the first device, the first interconnect structure includes a first metal layer, and the first metal layer includes a first connection branch. The second tier includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure includes a second metal layer, and the second metal layer includes a second connection branch. The through tier via is electrically coupled to the first and second connection branches.

An electronic component including a first device die hybrid bonded to a carrier, an encapsulant encapsulating side surfaces of the first device die and a cover element disposed over directly bonded to a top surface of the first device die. The encapsulant comprises particles embedded therein, and wherein an interface between a top surface of the encapsulant and a bottom surface of the cover element lacks ground particles

The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.

The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.

A semiconductor module includes a first semiconductor chip including a first surface and a second surface parallel to a first direction and a second direction, a sub-semiconductor cube including a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip stacked in the first direction, and a semiconductor cube arranged on the second surface, wherein the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, a plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be able to communicate contactlessly using the plurality of first inductors and the plurality of second inductors.

A semiconductor module includes a first semiconductor chip including a first surface and a second surface parallel to a first direction and a second direction, a sub-semiconductor cube including a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip stacked in the first direction, and a semiconductor cube arranged on the second surface, wherein the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, a plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be able to communicate contactlessly using the plurality of first inductors and the plurality of second inductors.