The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A semiconductor package including a substrate, a chip stack stacked on a top surface of the substrate, and a mold layer provided on the top surface of the substrate and the chip stack is provided. The chip stack include a first chip having a first region provided with chip pads and second regions provided at a first side and a second side of the first region. The chip pads of the first chip may be bonded to substrate pads of the substrate to form a single object. Each of the second regions of the first chip may be spaced apart from the top surface of the substrate in a direction perpendicular to the top surface of the substrate. The mold layer may fill a space between each of the second regions and the top surface of the substrate.

The disclosure relates to a display device and an anisotropic conductive film. An anisotropic conductive film disposed between a display panel and a printed circuit board, the anisotropic conductive film including a base resin, a plurality of first conductive balls dispersed in the base resin, each of the plurality of first conductive balls including a core made of a polymer material and at least one metal layer surrounding the core, and a plurality of second conductive balls dispersed in the base resin, each of the plurality of second conductive balls being made of a meltable material, and the anisotropic conductive film having a first area in which the anisotropic conductive film overlaps the first pad electrode and the first lead electrode in a thickness direction of the display device, and a second area as an area disposed between the first lead electrode and the second lead electrode. Each of the metal layer of the first conductive ball and a surface of the second conductive ball are in contact with both the first pad electrode and the first lead electrode.

A sensor package structure with no air cavity therein and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a sensing module disposed on the substrate, and an opaque encapsulant that is formed on the substrate. The sensing module includes a sensor chip mounted on the substrate, a first transparent adhesive layer adhered to the sensor chip, and a first glass that is adhered to the first transparent adhesive layer. The sensor chip is electrically coupled to the substrate, and the first transparent adhesive layer is stacked on a sensing region of the sensor chip. The sensing module is embedded in the opaque encapsulant, and an outer surface of the first glass is at least partially exposed from the opaque encapsulant.

Provided are an electronic package and an electronic structure. The electronic package includes a carrier, an electronic component disposed on the carrier, a heat dissipation member connected to the electronic component through a thermal interface material, a backside metal layer disposed on the electronic component and connected to the thermal interface material, and a nanowire array metal layer disposed between the thermal interface material and the backside metal layer. Therefore, a displacement of the thermal interface material relative to the backside metal layer is limited by a rough surface of the nanowire array metal layer. As such, a migration of the thermal interface material and a resulting poor bonding between the heat dissipation member and the electronic component, which affect a heat dissipation efficiency of the electronic package, can be prevented.

A device includes: a first substrate; a second substrate; interconnects bonding the first substrate to the second substrate; and a polymer brush-based underfill layer in a gap between the first substrate and the second substrate. A method includes: attaching initiator molecules to one or more surfaces in a gap between a first substrate and a second substrate of a bonded structure, where the first substrate and the second substrate are bonded by interconnects; growing polymer chains from the initiator molecules; and annealing the bonded structure to form an underfill layer from the polymer chains in the gap.