A thermal conduction sheet holder include, in the following order, an elongated carrier film, a plurality of thermal conduction sheets, and an elongated cover film covering the plurality of thermal conduction sheets, the shortest distance between adjacent thermal conduction sheets is 2 mm or more, the plurality of thermal conduction sheets are disposed at intervals in a longitudinal direction of the carrier film and the cover film, and the plurality of thermal conduction sheets are peelable from the cover film and the carrier film.

A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

In one example, a semiconductor device includes a conductive structure having a conductive structure upper side. A roughening is on the conductive structure upper side and a groove is in the conductive structure extending partially into the conductive structure from the conductive structure upper side. An electronic component is attached to the conductive structure upper side with an attachment film. An encapsulant covers the electronic component, at least portions of the roughening, and at least portions of the conductive structure upper side. The groove has smoothed sidewalls that include substantially planarized portions of the roughening. The smooth sidewalls reduce flow of the attachment film across the conductive structure upper side to improve adhesion of the encapsulant to the conductive structure. Other examples and related methods are also disclosed herein.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A current sensor integrated circuit (IC) package is flip-chip bonded using a conductive film to connect the IC circuit bond pads to the lead frame. A conductive film is positioned between the die surface of a semiconductor die and at least one signal lead of the lead frame. The conductive film is conductive in a first direction between the die and the signal lead and nonconductive in other directions. The conductive film is further configured to control a gap height between the die and the lead frame to reduce die tilt, thus improving the sensitivity and performance consistency of the package.

Provided is a semiconductor package including a plurality of first semiconductor chips respectively including a first semiconductor substrate and a plurality of first through electrodes penetrating the first semiconductor substrate, a second semiconductor chip on the plurality of first semiconductor chips, the second semiconductor chip including a second semiconductor substrate and a plurality of second through electrodes penetrating the second semiconductor substrate, a third semiconductor chip on the second semiconductor chip, the third semiconductor chip including a third semiconductor substrate and a plurality of third through electrodes penetrating the third semiconductor substrate, and a first encapsulation material on the plurality of first semiconductor chips, a planar shape of the second semiconductor chip is greater than a planar shape of each first semiconductor chip of the plurality of first semiconductor chips, and a planar shape of the third semiconductor chip is greater than the planar shape of the second semiconductor chip.

A method of fabricating an electronic device includes forming an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

An electronic device according to the present invention includes: a semiconductor chip that is mounted on a substrate; a heat sink that is attached to the substrate so as to face the upper surface of the semiconductor chip; a liquid metal that comes into contact with the upper surface of the semiconductor chip and the lower surface of the heat sink; seal members that are provided so as to surround the liquid metal and that seal an area between the upper surface of the substrate and the lower surface of the heat sink; and communication sections that are provided in the heat sink and communicate the internal space surrounded by the seal members, the semiconductor ship, and the heat sink, with the outside of the heat sink.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.