An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

Described herein is a method of using a composition for selectively etching a silicon layer in the presence of a layer including a silicon germanium alloy, the composition including: (a) 4 to 15% by weight of an amine of formula (E1), and (b) water, where X.sup.E1, X.sup.E2, and X.sup.E3 are independently selected from a chemical bond and C.sub.1-C.sub.6 alkanediyl; Y.sup.E is selected from N, CR.sup.E1, and P; R.sup.E1 is selected from H and C.sub.1-C.sub.6 alkyl.

A substrate processing method processes a substrate. The substrate has a major surface including a concave-portion forming surface that forms a concave portion. A to-be-removed layer is formed in the concave portion. The substrate processing method includes an etching step of supplying an etching liquid that contains etching ions to the major surface of the substrate to etch the to-be-removed layer, a concentrating step of concentrating the etching liquid on the major surface of the substrate, a hydrophilizing step of hydrophilizing the concave-portion forming surface exposed by concentrating the etching liquid, an ion diffusing step of diffusing the etching ions into a rinsing liquid by supplying the rinsing liquid to the major surface of the substrate after the hydrophilizing step, and a rinsing liquid removing step of removing the rinsing liquid from the major surface of the substrate.

A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.

A substrate processing apparatus includes a substrate processing unit for processing a substrate by discharging a chemical liquid to the substrate; a chemical storage unit connected to the substrate processing unit by a chemical liquid supply line and a chemical liquid recovery line; and a liquid replenishment unit including an evaporation measurement member for measuring the amount of evaporation of water contained in the chemical liquid, and a water supply member for supplying water to the chemical liquid.

Provided is a treatment liquid for a semiconductor with ruthenium including a ligand which coordinates to ruthenium, the treatment liquid is a treatment liquid for inhibiting a ruthenium-containing gas generated when contacting a semiconductor wafer including ruthenium with the treatment liquid in a semiconductor forming process. Also provided is an inhibitor for the generation of a ruthenium-containing gas, including a compound having a carbonyl group or a heterocyclic compound. Further provided is a treatment agent for a ruthenium-containing waste liquid, including a compound having a carbonyl group or a heterocyclic compound.

The present disclosure provides etching compositions that can selectively etch TiN in the presence of a variety of other layers, such as, for example, W, AlO.sub.x, and interlayer dielectrics (ILD).

Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.