The present application provides a method for fabricating multiple work function layers, including: forming the first to the nth transistor gates with notches; forming a blocking layer in the notches; depositing the first work function layer and removing the first work function layer on the first to the (n1)th transistor gates; depositing a second work function layer; removing the second work function layer on the first to the (n2)th transistor gates; depositing a third work function layer on the blocking layer on the first to the (n2)th transistor gates and the second work function layer on the (n1)th and nth transistor gates; removing the third work function layer on the first to (n3)th transistor gates; depositing the third to the (n1)th work function layers by analogy until only the blocking layer exists on the last transistor gate, herein the thickness of the third to the (n1)th work function layers decreases sequentially and gradually.

Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include exposing an edge region to treatment gases such as etch gases and/or inhibition gases. Also provided herein are exclusion ring assemblies including multiple rings that may be implemented to provide control of the processing environment at the edge of the wafer.

A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.

The present application discloses a support bracing structure, a semiconductor device with the support bracing structure, and a method for fabricating the semiconductor device with the support bracing structure. The support bracing structure includes a first bracing layer including two connection portions respectively positioned on top surfaces of two adjacent bottom electrodes, and a frame portion bridging the two connection portions; and a protection layer including a first portion positioned on and conforming to an inner surface of the frame portion and positioned between the two connection portions. The inner surface of the frame portion is normal to the top surfaces of the two adjacent bottom electrodes.

A topology-selective deposition method is disclosed. An exemplary method includes providing an inhibition agent comprising a first nitrogen-containing gas, providing a deposition promotion agent comprising a second nitrogen-containing gas to form an activated surface on one or more of a top surface, a bottom surface, and a sidewall surface relative to one or more of the other of the top surface, the bottom surface, and the sidewall surface, and providing a precursor to react with the activated surface to thereby selectively form material comprising a nitride on the activated surface.

A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Disclosed are methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

A capacitor is provided. The capacitor includes a first electrode, a second electrode disposed to face the first electrode, a dielectric layer of a rutile phase, disposed between the first electrode and the second electrode, and an interface layer between the first electrode and the dielectric layer, wherein the interface layer includes a first interface layer and a second interface layer, the first interface layer is adjacent to the first electrode, the second interface layer is adjacent to the dielectric layer, the first interface layer includes a conductive metal oxide having a work function in a range of about 4.8 eV to about 6.0 eV, the second interface layer includes a metal oxide having a rutile-phase crystal structure, and a thickness of the second interface layer is smaller than a thickness of the first interface layer.