Patent classifications
H10P14/69392
METHOD FOR MANUFACTURING METAL FLUORIDE-CONTAINING ORGANIC POLYMER FILM, PATTERNING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a metal fluoride-containing organic polymer film includes forming an organic polymer film on a base body. The method includes exposing the organic polymer film to an organometallic compound containing a first metal, thereby infiltrating the organic polymer film with the organometallic compound. The method includes exposing the organic polymer film infiltrated with the organometallic compound to hydrogen fluoride, thereby providing a fluoride of the first metal in the organic polymer film.
Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.
SEMICONDUCTOR CAPACITOR AND METHOD OF FORMING THE SAME
The present disclosure provides a semiconductor capacitor. The semiconductor capacitor includes a first conductive layer, a second conductive layer and a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer, and the first conductive layer and/or the second conductive layer are performed a plasma treatment to remove impurities therein and replace the impurities with nitrogen atoms. In addition, a method of forming a semiconductor capacitor is also disclosed.
CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES
Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.
HIGH BANDWIDTH PACKAGE STRUCTURE
A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.
Method for producing a ferroelectric layer or an antiferroelectric layer
A method for producing a ferroelectric layer or antiferroelectric layer in which a layer of a paraelectric material already deposited on a surface of a substrate with a layer thickness of at least two crystallographic unit cells is introduced into an alternating electric field. The alternating electric field is repeatedly cycled between a positive electric field strength and a negative electric field strength of amplitude greater than the coercivity field strength of the material such that the layer of paraelectric material forms a polarization.
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.
Semiconductor device including capacitor and method for fabricating the same
A method for fabricating a semiconductor device includes: forming a first oxide layer containing a first element over a first electrode layer; forming a second oxide layer containing a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the first oxide layer and the forming of the second oxide layer a plurality of times; and forming a second electrode layer over the stacked structure, wherein a thickness of a lowermost first oxide layer among the plurality of first oxide layers is greater than a thickness of each of other first oxide layers.
CHARGE COMPENSATION IN A SEMICONDUCTOR DEVICE
A method for forming a charge balance region in a semiconductor device includes: providing an epitaxial layer on a substrate, whereby a diffusion layer is formed between the substrate and the epitaxial layer; forming a plurality of recessed features extending in a vertical direction in the epitaxial layer and laterally spaced apart from one another; forming an insulating layer on at least sidewalls of each of the recessed features; and forming a resistive film on the insulating layer and a bottom of each of the recessed features using atomic layer deposition. The resistive film is configured to provide a conductive path between an upper surface of the epitaxial layer and one of the diffusion layer, a lower portion of the epitaxial layer, or the substrate, whereby a current flowing through the resistive film fully depletes at least a portion of the epitaxial layer between adjacent recessed features.
Generating a low-temperature substrate protective layer
A method for depositing protective layers on a surface of a substrate includes conducting a plurality of ALD cycles in a first reaction chamber to deposit a first protective layer on the substrate. Each ALD cycle of the plurality of ALD cycles is conducted at a deposition temperature below about 100 C. and includes delivering a first precursor gas into the first reaction chamber containing the substrate. A reacting portion of the first precursor gas is absorbed onto a surface of the substrate to form a first sub-layer of the protective layer. A second precursor gas is delivered into the first reaction chamber containing the substrate, a reacting portion of the second precursor gas being absorbed onto the surface of the substrate to form a second sub-layer of the protective layer. Metrology analysis is performed on the substrate within a second reaction chamber.