A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion with a continuous sidewall. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. A second element has a second nonconductive field region and a second conductive feature which are directly bonded to the first nonconductive field region and a first conductive feature, respectively.

A manufacturing method for a semiconductor device includes: obtaining a pre-processed semiconductor structure, wherein the pre-processed semiconductor structure comprises a metal layer (103) having a first exposed surface (1032), and the first exposed surface (1032) of the metal layer has a protrusion portion (1031); arranging a protective layer (104) on the first exposed surface (1032) of the metal layer, wherein the protective layer (104) at least covers part of the metal layer (103) that excludes the protrusion portion (1031); removing the protrusion portion (1031) to form on the metal layer (103) a second exposed surface (1033) of the metal layer (103); and forming a dielectric layer (105) on an area where the first exposed surface (1032) is located, wherein the dielectric layer (105) completely covers the area where the first exposed surface (1032) is located.

A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, and a plurality of through-electrodes extending through the first substrate and connected to the plurality of first pads, and a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, and a plurality of second pads below the second substrate and in contact with the plurality of first pads. The plurality of first pads includes a first group of first pads each including a first base layer including a first recess, and a first conductive pattern layer and a first insulating pattern layer alternately disposed in the first recess, and a second group of first pads each including a second base layer including a second recess, and a second conductive pattern layer disposed in the second recess.

An electronic component is disclosed. In one example, the electronic component comprises a semiconductor body, an active region in the semiconductor body, at least one metallization structure arranged on or above the active region and comprising a stack. The stack includes a barrier structure, an intermediate structure on the barrier structure and comprising nickel, and a copper and/or aluminium structure on the intermediate structure and comprising copper and/or aluminium. A dielectric structure is connected to a sidewall of the stack.

A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.