A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

A semiconductor device and method including depositing a passivation layer over an upper contact feature. In some embodiments, a polyimide (PI) layer is formed over the passivation layer. In an example, the PI layer is patterned to form a patterned PI layer including a first opening that exposes a portion of the passivation layer over the upper contact feature. In an embodiment, one or more etching processes are performed to form a second opening that exposes a top surface of the upper contact feature. In some embodiments, the one or more etching processes etches the passivation layer through the first opening to form a patterned passivation layer. In some examples, the one or more etching processes also recesses sidewall surfaces of the patterned PI layer from corners of the patterned passivation layer defined along opposing surfaces of the second opening.

A method of manufacturing interconnects for an electronic device includes the steps: a) providing a substrate having a first die, assembled to a second die by hybrid bonding, formed therein, and having conductive areas positioned on top of it, the second die comprising through silicon vias; b) forming conductive wires on the conductive areas, and optionally on the through silicon vias; c) depositing a layer of insulating material on the substrate and on the second die, to encapsulate the conductive wires; d) thinning the layer of insulating material; and e) forming conductive elements on the layer of insulating material, the conductive elements being connected either to the conductive areas or to the vias.

A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

Provided is a multi-dies stacking structure, which includes: a plurality of core dies stacked, wherein each core die comprises a first sub-core die and a second sub-core die vertically stacked; adjacent core dies are interconnected through micro-metal bumps, and the first sub-core die is interconnected with the second sub-core die through hybrid bonding members.

A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes an integrated circuit die, a dielectric layer, an under-bump metallurgy layer, an interconnection die, and a solder material. The integrated circuit die includes a first die connector. The dielectric layer is located on the integrated circuit die. The under-bump metallurgy layer has a line portion on the dielectric layer and a via portion extending through the dielectric layer to contact the first die connector. The interconnection die includes a second die connector. The solder material is located between the line portion of the under-bump metallurgy layer and the second die connector. The under-bump metallurgy layer includes a first copper layer having a uniform grain orientation, wherein the top surface of the first copper layer is in direct contact with the solder material.

Provided is a semiconductor device including a substrate, a semiconductor chip on the substrate, and a bonding layer between the substrate and the semiconductor chip, wherein the bonding layer includes a transition metal, a low-melting-point metal having a melting point lower than a melting point of the transition metal, a noble metal, and an alloy thereof, and a percentage of the noble metal in the bonding layer is greater in a central portion of the bonding layer than at peripheral portions of the bonding layer in a first direction of the bonding layer.

In some aspects, a device includes a substrate. A first metallization arranged on the substrate. A second metallization arranged on the substrate. A circuit arranged on the substrate and electrically connected to the first metallization and the second metallization. The first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device, where the substrate may include silicon carbide (SiC).

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop/interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop/interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.