A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A1) a polyglycerol having a weight average molecular weight of 350 to 2800 and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded. A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A2) a polyglycerol having a hydroxyl value of 800 to 1000 mgKOH/g and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded.

A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.

Cerium oxide particles for chemical mechanical polishing and a chemical mechanical polishing slurry composition comprising same are described. A combination of the characteristic cerium oxide particles with a dishing control agent leads to the provision of a chemical mechanical polishing slurry composition that suppresses dishing occurring during the polishing process while enhancing the oxide layer polishing rate, and a method for manufacturing semiconductor devices utilizing same.

A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.

A method of fabricating a semiconductor device includes forming a substrate and a wiring layer, forming a first interlayer insulating layer on the wiring layer, forming an etch stop layer covering a portion of an upper surface of the first interlayer insulating layer, forming a compensation insulating layer on the first interlayer insulating layer and the etch stop layer, planarizing the compensation insulating layer to form a compensation insulating pattern, forming a second interlayer insulating layer on the etch stop layer, and bonding the second interlayer insulating layer and a bonding wafer. The planarizing of the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

A planarization system is provided. The planarization system includes a first substrate chuck which holds the substrate during a planarization step, and a second substrate chuck which holds the substrate with a non-flat configuration during a separation step.

An electronic package and a manufacturing method thereof are provided. The electronic package includes a carrier structure, an electronic element, a bridge element, an encapsulation layer, and a photonic element. The electronic element and the bridge element are disposed on a second surface of the carrier structure to be electrically connected to the carrier structure. The encapsulation layer covers the electronic element and the bridge element. The photonic element is disposed on a surface of the encapsulation layer and is electrically connected to the bridge element. In the electronic package and the manufacturing method thereof, the photonic element is disposed after the formation and grinding of the encapsulation layer are completed, the photonic element can be prevented from covering by the encapsulation, thereby contamination or damage to the light transmitters and the light receivers of the photonic element can be avoided.

As an example, the present invention relates to a hybrid bonding method using an organic insulating layer as an insulating layer. In the hybrid bonding method using an organic insulating layer, there may be a difference in thermal expansion between a terminal electrode made of metal or the like and the organic insulating layer due to heating at the time of bonding, and it is necessary to provide a predetermined level difference D between a tip end surface of the terminal electrode and a surface of the organic insulating layer in advance. In the present invention, in order to provide the level difference D, the surface of the semiconductor substrate 100 is irradiated with plasma (e.g. argon plasma). In this plasma irradiation, an organic insulating layer 102 is etched with plasma such that a surface 102a of the organic insulating layer 102 of the semiconductor substrate 100 is on the farther side than a tip end surface 103a of an electrode 103.

The present disclosure provides means that can achieve a high polishing removal rate of a material having a silicon-silicon bond and can satisfy a ratio of a polishing removal rate of the material having a silicon-silicon bond to a polishing removal rate of a material having an oxygen-silicon bond within a good range, when the pH of a polishing composition is less than 7. The present disclosure relates to a polishing composition containing the following component (A) and the following component (B) and having a pH of less than 7; component (A): surface-modified silica particles containing silica particles and a surface-modifying group that modifies a surface of the silica particles and contains a polyoxyalkylene chain having a weight average molecular weight of 80 or more and 7,000 or less; and component (B): water.

A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern including staircases, each of the staircases including a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask as an etch mask to form a plurality of recesses, each of the plurality of recesses landing on each of the staircases, the ESL protecting the conductive surface from the etching, the etching including exposing the substrate to a plasma generated from a process gas including a fluorocarbon, O.sub.2, and WF.sub.6, a flow rate of WF.sub.6 being between 0.01% and 1% of a total gas flow rate of the process gas.