A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.

A semiconductor package includes a substrate including first bonding pads. At least one chip stack is on the substrate and includes a plurality of semiconductor chips stacked thereon. The semiconductor chips include first connection pads electrically connected to the first bonding pads, bonding wires electrically connecting the substrate to the chip stack, and connection bumps below the substrate. The semiconductor chips include a second group of semiconductor chips stacked on a first group of semiconductor chips. An uppermost semiconductor chip in the first group of semiconductor chips or a lowermost semiconductor chip in the second group of semiconductor chips further includes second connection pads electrically connected to the first connection pads, respectively. The bonding wires include first bonding wires electrically connecting the first connection pads of the semiconductor chips to each other, and second bonding wires electrically connecting the second connection pads and the first bonding pads to each other.

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

A switching module includes at least one substrate, at least one switching element, at least one control loop, a first power part and a second power part. The at least one switching element is disposed on the at least one substrate. The at least one control loop is connected with the corresponding switching element. The first power part is connected with the corresponding switching element. The second power part is connected with the corresponding switching element. A direction of a first current flowing through the first power part and a direction of a second current flowing through the second power part are identical. A projection of the first power part on a reference plane and a projection of the second power part on the reference plane are located at two opposite sides of a projection of the control loop on the reference plane.

A semiconductor module, including a semiconductor chip, a sealed main body portion sealing the semiconductor chip and having a pair of attachment holes penetrating therethrough, a heat dissipation plate in contact with the sealed main body portion. The heat dissipation plate is positioned between the attachment holes in a plan view of the semiconductor module. The semiconductor module further includes a pair of rear surface supporting portions and/or a pair of front surface supporting portions protruding respectively from rear and front surfaces of the sealed main body portion. In the plan view, the heat dissipation plate is formed between the pair of attachment holes, which are in turn between the pair of rear surface supporting portions. The pair of front surface supporting portions are formed substantially between the pair of attachment holes in the plan view.

A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.

An amplifier circuit that includes an RF amplifier; an impedance matching network; a higher order harmonic termination circuit; a fundamental frequency matching circuit; and an integrated passive device (IPD) that includes a silicon carbide (SiC) substrate. The integrated passive device (IPD) includes one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

A first gate pattern and a first source pattern are linearly formed in parallel to each other along a first edge of an insulating substrate. A second gate pattern is formed in a quadrangular shape in a top view, extending from the first edge side of the insulating substrate to a second edge side facing the first side. A drain pattern is formed to surround at least three edges of the quadrangular shape of the second gate pattern. A second source pattern is formed along an edge other than the first edge of the insulating substrate to surround the drain pattern. First and second semiconductor chip groups are arranged at positions adjacent to the second source pattern. The first and second semiconductor chip groups and the second source pattern are connected via a plurality of first source wires.