The semiconductor device includes a semiconductor element, a conductive support member and a sealing resin whose resin side surface faces one side of a first direction. The support member has an outer lead including a root portion extending from the resin side surface, a mount portion on one side of a thickness direction relative to the root portion, and an extended portion connected to the root portion via a bent portion and to the mount portion via another bent portion. The outer lead has a first division including the extended portion, a second division including the root portion and connected to the first division, and a third division including the mount portion and connected to the first division. The first division is greater in second-direction dimension than the second and third divisions. A division boundary between the first and the third divisions is at the extended portion.

A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

A power package includes at least one power substrate having at least one power trace, at least one power device on the at least one power trace, signal terminals, and at least one signal connection assembly. The at least one signal connection assembly includes at least one of the following: at least one signal trace that is thinner than the at least one power trace; at least one embedded routing layer within the at least one power substrate; and/or at least one routing layer on the at least one power substrate.

The electronic device includes a first electronic component, a second electronic component, a sealing resin covering the first/second electronic components, first, second, third and fourth leads, a first die pad supporting the first electronic component, and a second die pad supporting the second electronic component. The sealing resin has resin side surfaces facing in orthogonal directions perpendicular to a thickness direction of the sealing resin. A first outer portion of the first lead, a second outer portion of the second lead and a third outer portion of the third lead are exposed from one or more resin side surfaces different from the resin side surface from which a fourth outer portion of the fourth lead is exposed.

A semiconductor device includes a first die pad, a first semiconductor element, a first lead, a first conductive member, and a sealing resin. The first conductive member is conductively bonded to the first semiconductor element and the first lead. The first die pad, the first semiconductor element, and the first conductive member are covered with the sealing resin. The first lead protrudes from the first side surface of the sealing resin. The first distance D1, the second distance D2, and the third distance D3 satisfy the relationship D1>D2D3. In the first direction z, the first conductive member is located between the first mounting surface of the first die pad and the top surface of the sealing resin.

Power semiconductor device packages and methods for manufacturing the same are provided. In one example, a power semiconductor device package may include a housing, a submount, and a conjoined semiconductor die structure on the submount. The conjoined semiconductor die structure may include at least two semiconductor die having a common substrate. The conjoined semiconductor die structure may be cut from a semiconductor wafer and may be packaged based on die viability data indicative of an operability of each respective semiconductor die of the at least two semiconductor die.

A device may include a first chip and a second chip, the first chip and the second chip being connected by a set of wirebonds. The device may include a ground cover structure providing a ground over the set of wirebonds. The ground cover structure may include a dielectric structure having a cavity on a first side of the dielectric structure. The ground cover structure may include a metal structure on a second side of the dielectric structure. The ground cover structure may include a dielectric material within the cavity of the dielectric structure.

Within the cavity, each wirebond in the set of wirebonds may be encapsulated by the dielectric material or by a combination of the dielectric material and the dielectric structure.

A semiconductor module, including a first main wiring line connecting portion and a second main wiring line connecting portion, and a main output wiring line connecting portion is provided. The circuit board includes a circuit region in which the first circuit and the second circuit are arranged alongside each other in the first direction, and a first connecting region and a second connecting region arranged sandwiching the circuit region in a second direction orthogonal to the first direction. The first main wiring line connecting portion and the second main wiring line connecting portion are provided in the first connecting region, and the main output wiring line connecting portion is provided in the second connecting region.

The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a package includes first and second IC dice. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is on a substrate. The capacitor includes a bottom plate over the substrate and a top plate over the bottom plate. The polyimide layer is at least partially over the top plate. A distance from a top surface of the top plate to a bottom surface of the polyimide layer is at least 30% of a distance from a top surface of the bottom plate to a bottom surface of the top plate. A signal path, including the capacitor, is electrically coupled between the first circuit and a second circuit in the second IC die, which does not include a galvanic isolation capacitor in the signal path.

A semiconductor module, including: a semiconductor element; a wiring board on which the semiconductor element is mounted; a case that has a shape of a frame, to thereby form a housing space to house the semiconductor element and the wiring board; a terminal that is electrically connected to the wiring board; a lid that closes the housing space, the lid including a lid through-hole into which the terminal is inserted; an inner cover disposed in the housing space, the inner cover having an inner through-hole into which the terminal is inserted; and a sealing material disposed between the lid and the inner cover, and sealing the terminal.