Patent classifications
H10P72/744
MANUFACTURABLE GALLIUM AND NITROGEN CONTAINING SINGLE FREQUENCY LASER DIODE
A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.
Dynamic release tapes for assembly of discrete components
A method includes positioning a discrete component assembly on a support fixture of a component transfer system, the discrete component assembly including a dynamic release tape including a flexible support layer, and a dynamic release structure disposed on the flexible support layer, and a discrete component adhered to the dynamic release tape. The method includes irradiating the dynamic release structure to release the discrete component from the dynamic release tape.
Method for cleaning semiconductor substrate, method for producing processed semiconductor substrate, and stripping composition
A semiconductor substrate cleaning method including removing an adhesive layer provided on a semiconductor substrate by use of a remover composition, wherein the remover composition contains a solvent but no salt; and the solvent includes an organic solvent represented by any of formulae (L0) to (L4). ##STR00001##
Method for manufacturing semiconductor element, semiconductor element body, and semiconductor element substrate
A method of manufacturing a semiconductor element includes: forming a first semiconductor layer (SL1) and a second semiconductor layer (SL2) larger in thickness than the first semiconductor layer (SL1) on a mask layer (ML) including a first opening portion (K1) and a second opening portion (K2); forming a first device layer (DL1) and a second device layer (DL2); and bonding the first device layer (DL1) and the second device layer (DL2) to a support substrate (SK).
Semiconductor package and method of forming the same
A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.
FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS
A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.
INTEGRATION OF MICRODEVICES INTO SYSTEM SUBSTRATE
In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The microdevices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.
COMPACT ANCHOR
The present disclosure relates to methods of holding microdevices to the cartridge or donor substrate. Here an anchor layer and a release layer are on the donor substrate and the release layer is removed and a free standing anchor layer holds the microdevice. The present invention further relates to the process of microdevice transfer by reducing a bonding force by reducing the release layer area under the microdevice. Here etching and a blocking structure to control the etching rate may be used.
SYSTEMS AND METHODS FOR THREE-DIMENSIONA STACKING OF SEMICONDUCTOR DIES IN A STAGGERED PATTERN
Consistent with aspects of the present disclosure, fabrication processes are provided for manufacturing 3-D stacked dies in a staggered pattern. Such processes yield device structures having adequate flatness and provide sufficient alignment for effective hybrid bonding in staggered 3-D die stacked package.