A spectroscopic device may include a light source part configured to emit a first light toward a target object, the light source part including a main light source and a plurality of auxiliary light sources, a diffraction part including a diffraction grating configured to diffract a second light that is produced based on the first light being reflected from the target object, the diffraction grating configured to produce a third light that is the diffracted second light, a detection part configured to detect the third light, and an analyzing part connected to the detection part. The detection part may include a plurality of pixels and an actuator. The plurality of auxiliary light sources may be configured to emit light rays of different wavelengths. The actuator may be configured to rotate and move the detection part.

A method of producing a semiconductor device, the method includes steps of: detecting a defect included in a semiconductor layer; forming a metal film on the semiconductor layer; after forming the metal film on the semiconductor layer, exposing the semiconductor layer through the metal film by removing a portion of the metal film by irradiation with a first laser emitting red or infrared light; and after the step of exposing the semiconductor layer, removing a portion of the semiconductor layer by irradiation with a second laser emitting ultraviolet light, said portion of the semiconductor layer including the defect. A diameter of said portion of the metal film is greater than a diameter of said portion of the semiconductor layer in a plan view. Said portion of the metal film overlaps with said portion of the semiconductor layer in the plan view.

A method of processing a wafer includes forming a bonded wafer assembly by bonding one of opposite surfaces of a first wafer to a second wafer, the first wafer having a device region and an outer circumferential excessive region, applying a laser beam to the first wafer while positioning a focused spot of the laser beam radially inwardly from the outer circumferential edge of the first wafer, on an inclined plane that is progressively closer to the one of the opposite surfaces of the first wafer toward the outer circumferential edge, thereby forming a separation layer shaped as a side surface of a truncated cone, grinding the first wafer from the other one of the opposite surfaces thereof to thin down the first wafer to a predetermined thickness, and detecting whether or not the outer circumferential excessive region has been removed from the first wafer.

A method comprises determining a representative ground truth structure provided in a semiconductor sample having a plurality of structures extending mainly in a thickness direction of the sample in a region of interest containing the plurality of structures. At least one adapted image of a milled sample is determined, wherein the at least one adapted image comprises image representations of the structures in the region of interest at different positions in the thickness direction. A transformation is determined by which the image representations at the different positions in the thickness direction of the structures build the ground truth structure, and the transformation is stored for a future application of the transformation to a further sample having the plurality of structures.

A method for detecting impurities on a surface of a silicon wafer for manufacturing semiconductors, the impurities not being able to be detected by a conventional inspection method, a method for manufacturing the silicon wafer for manufacturing semiconductors having the impurities removed from the surface thereof, and a method for screening wafers for manufacturing semiconductors. This method for detecting impurities on a surface of a wafer for manufacturing semiconductors includes: a step for coating the surface of the wafer with a film-forming composition, and performing baking to form a film; and then a step for detecting impurities by means of a wafer inspection tool.

A method for detecting impurities on a surface of a silicon wafer for manufacturing semiconductors, the impurities not being able to be detected by a conventional inspection method, a method for manufacturing the silicon wafer for manufacturing semiconductors having the impurities removed from the surface thereof, and a method for screening wafers for manufacturing semiconductors. This method for detecting impurities on a surface of a wafer for manufacturing semiconductors includes: a step for coating the surface of the wafer with a film-forming composition, and performing baking to form a film; and then a step for detecting impurities by means of a wafer inspection tool.

A semiconductor package includes a first semiconductor chip including: a first substrate, a first wiring layer on a first surface of the first substrate, a plurality of first dummy pads electrically connected to each other by a redistribution layer disposed between the first wiring layer and a first passivation layer, and a plurality of second dummy pads disposed adjacent to the plurality of first dummy pads on the first wiring layer; and a second semiconductor chip including: a second substrate, a second wiring layer on the second substrate and opposite to the first surface of the first substrate, a plurality of third dummy pads having at least a portion that overlaps the plurality of first dummy pads on the second wiring layer, and a plurality of power pads arranged adjacent to the plurality of third dummy pads and configured to provide a test voltage.

Methods, systems, and media for deposition control in a process chamber are provided. In some embodiments, a method comprises (a) obtaining, at a present time, information indicating a status of one or more components of the process chamber during performance of a deposition process on one or more wafers. The method may comprise (b) determining whether adjustments to one or more control components of the process chamber are to be made by providing an input based on the obtained information to a trained machine learning model configured to determine adjustments as an output, wherein the adjustments to the one or more control components cause a change in the deposition process. The method may comprise (c) transmitting instructions to a controller of the process chamber that cause the adjustments to the one or more control components to be implemented.

A method can include bonding a first source die to a first destination site of a destination substrate, wherein the first source die includes a source metrology pattern including a source alignment mark, and the first destination site includes a destination metrology pattern including a destination alignment mark. The method can include collecting radiation data regarding the source and destination metrology patterns within a radiation area. The source alignment mark does not directly overlie or directly underlie any alignment mark of the destination metrology pattern. The method can further include analyzing the radiation data to determine an overlay error between the first source die and the first destination site; and adjusting a position of a second source die or a second destination site of the destination substrate to compensate for the overlay error between the first source die and the first destination site.

A matching method for semiconductor topography measurement and a processing device using the same are provided. The matching method includes the following steps. An original surface topography curve is obtained. The original surface topography curve is obtained by measuring along a measurement straight line path of a semiconductor device. The original surface topography curve is converted into a surface topography variation curve. A circuit layout is obtained. A plurality of conductor density variation curves are obtained along a plurality of layout straight-line paths. According to a plurality of weighted values of a plurality of topography variation observation intervals of the surface topography variation curve, a weighted correlation between the surface topography variation curve and each of the conductor density variation curves is analyzed. According to the weighted correlations, the measurement straight line path matching the original surface topography curve is obtained from the layout straight-line paths.