A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m.

A galvanic-isolation device includes a metal cap layer extending above a top metal layer of a galvanic isolation module. The metal cap layer is in electrical contact with the top metal layer at a central portion of the top metal layer. A buffer layer separates the metal cap layer from the top metal layer at peripheral portions of the top metal layer. Electric field peaks at edges of the metal cap layer and the top metal layer are decoupled from one another by recessing the lateral edges of the metal cap layer by a distance (for example, greater than one micrometer) from the corresponding edges of the top metal layer.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m; and electrically connecting the first landing pad to one of the two electrodes.

Electronic device including a primary capacitor extending on a semiconductor body accommodating a floating P-well and an N-type buried layer, to provide a P-N junction. This structure introduces a junction capacitance in series with the parasitic capacitance that the primary capacitor forms with the semiconductor body, effectively lowering the overall parasitic capacitance of the electronic device.

An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

An image sensor is provided. The image sensor includes a first semiconductor structure with photodiodes provided in a first semiconductor substrate, a first interconnection structure below the first semiconductor substrate, first bonding structures below the first interconnection structure and connected to the first interconnection structure, first shielding structures between the first bonding structures, and a first bonding insulating film surrounding lower regions of the first bonding structures and lower regions of the first shielding structures; and a second semiconductor structure a second interconnection structure provided in a second semiconductor substrate, second bonding structures contacting the first bonding structures on the second interconnection structure and connected to the second interconnection structure, second shielding structures between the second bonding structures and contacting the first shielding structures, and a second bonding insulating film surrounding upper regions of the second bonding structures and upper regions of the second shielding structures.

A thin film transistor array substrate includes a base substrate, a light shielding layer, a semiconductor layer, a gate insulating layer, a gate layer, and a source-drain metal layer in contact with the semiconductor layer and in contact with the light shielding layer sequentially disposed on the base substrate, a first insulating layer covering the source-drain metal layer disposed on the base substrate, and a metal protection layer disposed on the first insulating layer. The semiconductor layer, the gate layer, and the source-drain metal layer form a thin film transistor. An end of the metal protection layer is in contact with the source-drain metal layer, and another end of the metal protection layer is in contact with the light shielding layer.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a capacitor component, an inductor component, and an interconnect structure. The capacitor component is disposed over the substrate and includes an anode assembly and a cathode assembly electrically insulated from the anode assembly. The inductor component is disposed on and vertically aligned with the capacitor component, wherein the inductor component includes a signal line and a shielding assembly between the signal line and the capacitor component. The interconnect structure is disposed over the substrate and surrounds the capacitor component and the inductor component.

An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.