A method of manufacturing a semiconductor structure includes forming bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; forming a layer stack including a plasma treated oxygen-rich ARC layer and a silicon-rich ARC layer on the dielectric layer; forming a patterned mask layer including a mask feature and an opening on the layer stack, the opening has a first width smaller than a pitch between adjacent two of the bit line structures; trimming the patterned mask layer to enlarge the opening such that the opening has a second width greater than the first width; patterning the layer stack by using patterned mask layer as a mask after trimming the patterned mask layer; and etching the substrate to form a contact hole between the bit line structures by using the patterned layer stack as a hard mask.

Methods and systems for forming a structure including multiple carbon layers and structures formed using the methods or systems are disclosed. Exemplary methods include forming a first carbon layer with an initial first flowability and a second carbon layer with an initial second flowability, wherein first flowability is less than second flowability.

An amorphous silicon layer or amorphous boron layer can be deposited on a substrate using one or more silicon or boron-containing precursors, respectively. Radical species are provided from a plasma source or from a controlled reaction chamber atmosphere to convert the amorphous silicon layer to a doped silicon layer with composition tunability. An initiation layer is deposited on one or more semiconductor device structures having a dielectric layer over an electrically conductive layer. The initiation layer may be conformally deposited by a CVD-based process and may comprises amorphous silicon, doped silicon, amorphous boron, or doped boron.

Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

Exemplary semiconductor processing methods may include providing one or more first etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A plurality of pairs of silicon oxide material and polysilicon material may be disposed on the substrate. The methods may include forming plasma effluents of the one or more first etchant precursors and contacting the substrate with the plasma effluents of the one or more first etchant precursors to selectively etch silicon oxide material. The methods may include providing one or more second etchant precursors to the processing region, forming plasma effluents of the one or more second etchant precursors, and contacting the substrate with the plasma effluents of the one or more second etchant precursors to selectively etch polysilicon material. A temperature within the processing region may be greater than or about 0 C.

A method includes forming a mask over a semiconductor layer. The method includes first patterning the mask to form a first opening that exposes a first portion of the semiconductor layer. The method includes performing a plasma treatment to form a surface modification layer over the exposed first portion. The method includes second patterning the mask to form a second opening that exposes a second portion of the semiconductor layer, thereby forming a patterned mask that defines the first and second openings. The method includes performing an etching process to the semiconductor layer through the patterned mask to form a first trench extending from the first opening and a second trench extending from the second opening. The etching process removes the first portion at a first rate and the second portion at a second rate that is greater than the first rate.

A method for developing a passivation film on a substrate with less than 10 atomic % of hydrogen includes providing the substrate within a processing station of a substrate processing system. A resultant passivation film is formed with less than 10 atomic % of hydrogen on the substrate by performing the following steps of depositing a passivation film sub-layer on the substrate, where the passivation film sub-layer lays on a semiconductor device layer or directly on a previously deposited passivation film sub-layer, and after depositing the passivation film sub-layer, performing a post plasma treatment to the passivation film sub-layer with at least one of nitrogen and argon to reduce hydrogen content within the passivation film sub-layer.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.

Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Embodiments include semiconductor processing methods to form dielectric films on semiconductor substrates are described. The methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include providing an inert precursor to the processing region of the semiconductor processing chamber. The methods may include generating plasma effluents of the silicon-containing precursor, the nitrogen-containing precursor, and the inert precursor. The methods may include depositing a silicon-containing material on the substrate.