A semiconductor device package includes an interconnect structure with a first surface having at least one die thereon and a second surface that is opposite the first surface and is configured to be coupled to an external device. A protective structure on the first surface of the interconnect structure exposes a heat dissipating surface facing away from the interconnect structure in one or more directions. Related devices and fabrication methods are also discussed.

According to an example aspect of the present invention, there is provided a wafer-level package (1), comprising a top substrate (10) and a bottom substrate (30), wherein the top substrate (10) comprises a recess (12) on a side of the top substrate (10) which is towards the bottom substrate (30) and the bottom substrate (30) comprises a recess (32) on a side of the bottom substrate (30) which is towards the top substrate (10), wherein the recess (12) of the top substrate (10) and the recess (32) of the bottom substrate (30) are arranged to form a waveguide (5) within the wafer-level package (1) and a middle substrate (20) arranged to couple an integrated circuit (24) of the wafer-level package (1) to the waveguide (5), wherein the middle substrate (20) is in between the top substrate (10) and the bottom substrate (30) and the middle substrate (20) comprises a probe (21), wherein the probe (21) extends to the waveguide (5) and the probe (21) is arranged to couple a signal coming from the integrated circuit (24) to the waveguide (5), or to couple a signal coming from the waveguide (5) to the integrated circuit (24).

Methods and systems related to chip-to-chip electrical connection interfaces are disclosed. The electrical connections can be formed between chiplets, chip-scale packages, or unpackaged die. The electrical connection can serve as a physical connection to support various interface protocols such as the Bunch of Wires (BoW) or Universal Chiplet Interconnect Express (UCIe) protocols. An electrical connection interface comprises a first die connection for a first die, a first tuning block, a first escape region connection coupling the first die connection to the first tuning block, a second die connection for a second die, a second tuning block, a second escape region connection coupling the second die connection to the second tuning block, and a main trace coupling the first tuning block to the second tuning block.

A device includes a Doherty amplifier having a first amplifier die having a first output terminal, and a second amplifier die with a second output terminal. A device may include an output impedance matching network connected to an output terminal of the Doherty amplifier. A device may include an impedance inversion element connected to the second output terminal of the second amplifier die. A device may include a first wirebond array connected between the first output terminal of the first amplifier die and the output impedance matching network. A device may include a second wirebond array connected between the first output terminal of the first amplifier die and the impedance inversion element, wherein wirebonds of the first wirebond array are interleaved with wirebonds of the second wirebond array.

Disclosed in the present invention are an electromagnetic shielding structure, a manufacturing method and a communication terminal. The electromagnetic shielding structure comprises a module substrate, which is formed with a plurality of grounding holes penetrating through the module substrate, and the plurality of grounding holes jointly define a mounting area; a device to be shielded, which is attached to the module substrate and located in the mounting area; a plurality of grounding bonding pads, which are respectively arranged in the grounding holes in a penetrating manner; and a plurality of wires, wherein the two ends of each wire are respectively connected to two different grounding bonding pads, such that the plurality of wires jointly form a shielding layer erected above the device to be shielded.

A transistor according to the disclosure includes a semiconductor substrate, a source pad provided on an upper surface of the semiconductor substrate, a plurality of source electrodes provided on the upper surface of the semiconductor substrate and arranged in an arrangement direction, the plurality of source electrodes each including a first end connected to the source pad and a second end on a side opposite to the source pad, a plurality of drain electrodes arranged alternately with the plurality of source electrodes in the arrangement direction, a gate electrode and a first wire configured to connect the second ends of a plurality of central electrodes provided at a central part of the semiconductor substrate in the arrangement direction among the plurality of source electrodes, and not to connect the second ends of the source electrodes other than the plurality of central electrodes.

A Doherty amplifier according to the present disclosure includes an input terminal, an output terminal, a carrier amplifier connected between the input terminal and the output terminal, a peak amplifier connected in parallel to the carrier amplifier between the input terminal and the output terminal, a first input matching circuit connected between the input terminal and the carrier amplifier and a second input matching circuit connected between the input terminal and the peak amplifier, wherein the carrier amplifier and the peak amplifier output signals toward outside in directions opposite to each other.