A semiconductor device includes: an MMIC having a DC pad; a bias substrate; a plurality of MIM capacitors mounted on the bias substrate; a plurality of pads provided on the bias substrate and respectively connected to overlying electrodes of the MIM capacitors; and a wire connecting the DC pad to any one of the plurality of pads, wherein the plurality of pads are arranged between the DC pad and the plurality of MIM capacitors in a planar view, and extend parallel to a row of the plurality of MIM capacitors laterally arranged side by side.

In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.

A packaging device is provided. The packaging device includes a die disposed over a laminate, the die comprising a first via structure, and an interposer disposed between the die and the laminate. The interposer includes a second via structure. The packaging device also includes a lid disposed over the interposer and covering the die, a first patterned conductive layer disposed between the die and the interposer, and between the lid and the interposer; and a second patterned conductive layer disposed between the laminate and the interposer. The first patterned conductive layer includes a bonding structure electrically and thermally connected to the first via structure and the second via structure.

According to an example aspect of the present invention, there is provided a wafer-level package (1), comprising a top substrate (10) and a bottom substrate (30), wherein the top substrate (10) comprises a recess (12) on a side of the top substrate (10) which is towards the bottom substrate (30) and the bottom substrate (30) comprises a recess (32) on a side of the bottom substrate (30) which is towards the top substrate (10), wherein the recess (12) of the top substrate (10) and the recess (32) of the bottom substrate (30) are arranged to form a waveguide (5) within the wafer-level package (1) and a middle substrate (20) arranged to couple an integrated circuit (24) of the wafer-level package (1) to the waveguide (5), wherein the middle substrate (20) is in between the top substrate (10) and the bottom substrate (30) and the middle substrate (20) comprises a probe (21), wherein the probe (21) extends to the waveguide (5) and the probe (21) is arranged to couple a signal coming from the integrated circuit (24) to the waveguide (5), or to couple a signal coming from the waveguide (5) to the integrated circuit (24).

A microwave device can include: a first multilayer resin substrate including a ground via hole; a semiconductor substrate at the first multilayer resin substrate and including a high frequency circuit; a conductive heat spreader at an opposite face of the semiconductor substrate from a face of the semiconductor substrate facing the first multilayer resin substrate; a resin over the first multilayer resin substrate and covering the semiconductor substrate and the heat spreader such that an opposite face of the heat spreader from a face of the heat spreader facing the semiconductor substrate is exposed as an exposed face; and a conductive film covering the resin and the heat spreader and touching the exposed face. The semiconductor substrate can include a ground through hole extending through the semiconductor substrate. The conductive film can be electrically connected to the ground via hole via the heat spreader and the ground through hole.

Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.

An integrated electronic device includes at least one component produced on a carrier structure including a semiconductor substrate, and an interconnection track (8) that runs over the carrier structure from the component to a lateral face of the device. The interconnection track includes a layer of oxidizable material bearing a continuous layer of conductive material. The layer of oxidizable material is discontinuous. A method for producing such an integrated electronic device is also disclosed herein.