A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. A DTI region is formed in a trench that penetrates through the p-type semiconductor layer and the n-type buried layer, reaching the p-type substrate region. A plurality of scallops are formed at a side surface of the trench. A size of each of a plurality of first scallops formed at the side surface of the trench in the p-type semiconductor layer is larger than a size of each of a plurality of second scallops formed at the side surface of the trench in the n-type buried layer.

A method is provided for fabricating an interconnection structure. A first metal layer is formed over a semiconductor substrate. The first metal layer is patterned to form a first metal line and a second metal line. An interlayer dielectric layer is deposited over the first metal line and the second metal line, where the interlayer dielectric layer has a first air gap disposed between the first metal line and the second metal line. A via hole is formed in the interlayer dielectric layer, where the via hole exposes the first metal line. A metal via is formed in the via hole.

A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.

Embodiments of the present disclosure generally relate to metal gate devices. In one or more embodiments, a method for preparing a device with an airgap is provided and includes depositing a silicon-containing layer on inner surfaces of trenches formed in a metal-gate layer disposed on a substrate, depositing a carbon-containing layer on the silicon-containing layer in the trenches, the carbon-containing layer is deposited to fill at least a lower half of the trenches from the bottom, and leaving a temporary gap within each trench at the top. The method also includes depositing a low-k dielectric layer on the carbon-containing layer and the silicon-containing layer to fill the temporary gap, and exposing at least the carbon-containing layer to a treatment process to remove the carbon-containing layer and form the airgap between the silicon-containing layer and the low-k dielectric layer.

A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.