Described herein is a method of using a composition for selectively etching a silicon layer in the presence of a layer including a silicon germanium alloy, the composition including: (a) 4 to 15% by weight of an amine of formula (E1), and (b) water, where X.sup.E1, X.sup.E2, and X.sup.E3 are independently selected from a chemical bond and C.sub.1-C.sub.6 alkanediyl; Y.sup.E is selected from N, CR.sup.E1, and P; R.sup.E1 is selected from H and C.sub.1-C.sub.6 alkyl.

Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Electronic devices are formed on donor substrates and transferred to carrier substrates by forming bonding regions on the electronic devices and bonding the bonding regions to a carrier substrate. The transfer process may include forming anchors and removing sacrificial regions.

Described examples include a method for forming an integrated circuit, the method including depositing a metal layer including aluminum and copper over a semiconductor substrate and forming a patterned photoresist layer over the metal layer. The method also including etching the metal layer to produce a patterned metal layer and ashing the patterned photoresist layer in a plasma provided in a process chamber sourced with a gas flow having an N2/O2 ratio of at least 15%.

A substrate processing method using a substrate processing apparatus which comprises a process chamber in which a reaction space is formed to process a substrate in which a composite layer pattern having a plurality of first insulating layers and a plurality of second insulating layers alternately stacked thereon is formed, a substrate support unit, a gas distribution unit, and a plasma reactor, the method comprising the steps of: heating the substrate support unit and the gas distribution unit such that a temperature of the gas distribution unit is maintained equal to or lower than a temperature of the substrate support unit; supplying a reactive gas including a halogen-containing gas to the plasma reactor; generating radicals by applying power to the plasma reactor to activate the halogen-containing gas; and at least partially etching the plurality of first insulating layers in a lateral direction selectively with respect to the plurality of second insulating layers by supplying the radicals onto the substrate mounted on the substrate support unit through the gas distribution unit.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

A substrate processing method includes providing a substrate formed with a stacked film including at least an etching target film, an underlying layer disposed below the etching target film, and a mask disposed above the etching target film; etching the etching target film through the mask using plasma; and performing heat treatment on the substrate at a predetermined temperature after the etching. At least one of the mask and the underlying layer contains a transition metal.

The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

A manufacturing method of a semiconductor device includes forming a van der Waals structure between a metal and a semiconductor. The method further includes: depositing a protective layer on a two-dimensional semiconductor layer, then patterning the protective layer and the two-dimensional semiconductor layer, forming a first electrode and a second electrode on the protective layer, and removing the protective layer completely, thereby forming a van der Waals contact structure between the first electrode and the semiconductor layer and between the second electrode and the semiconductor layer.