SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A manufacturing method of a semiconductor device includes forming a van der Waals structure between a metal and a semiconductor. The method further includes: depositing a protective layer on a two-dimensional semiconductor layer, then patterning the protective layer and the two-dimensional semiconductor layer, forming a first electrode and a second electrode on the protective layer, and removing the protective layer completely, thereby forming a van der Waals contact structure between the first electrode and the semiconductor layer and between the second electrode and the semiconductor layer.

Claims

1. A manufacturing method of a semiconductor device, comprising the following steps: forming a two-dimensional semiconductor layer on a substrate; depositing a protective layer on the two-dimensional semiconductor layer; patterning the protective layer and the two-dimensional semiconductor layer; forming a first electrode and a second electrode on a portion of the protective layer and the substrate; and removing the protective layer completely to form a van der Waals contact structure between the first electrode and the two-dimensional semiconductor layer and between the second electrode and the two-dimensional semiconductor layer.

2. The manufacturing method of claim 1, wherein a method of forming the van der Waals contact structure comprises: removing the protective layer using an isotropic etching method or an anisotropic etching method; and collapsing the first electrode and the second electrode onto the two-dimensional semiconductor layer.

3. The manufacturing method of claim 1, wherein a method of patterning the protective layer and the two-dimensional semiconductor layer comprises: forming a patterned mask on the protective layer using a photolithography process; and removing the protective layer and the two-dimensional semiconductor layer not blocked by the patterned mask via etching.

4. The manufacturing method of claim 1, wherein a method of forming the first electrode and the second electrode comprises: depositing a metal film on the protective layer; and removing a portion of the metal film via dry etching or wet etching.

5. The manufacturing method of claim 4, wherein the metal film comprises a single layer or several layers of a metal film formed by chemical vapor deposition or physical vapor deposition.

6. The manufacturing method of claim 1, wherein a method of removing the protective layer completely comprises isotropic etching or anisotropic etching.

7. The manufacturing method of claim 1, wherein the protective layer comprises an oxide or nitride dielectric material.

8. The manufacturing method of claim 1, wherein a method of depositing the protective layer comprises using a physical vapor deposition method or a chemical vapor deposition method.

9. The manufacturing method of claim 1, wherein a material of the two-dimensional semiconductor layer comprises a tungsten disulfide (WS.sub.2), molybdenum disulfide (MoS.sub.2), tungsten diselenide (WSe.sub.2), molybdenum ditelluride (MoTe.sub.2), tungsten ditelluride (WTe.sub.2), or molybdenum diselenide (MoSe.sub.2) layered structure material.

10. The manufacturing method of claim 1, wherein a method of forming the two-dimensional semiconductor layer on the substrate comprises: physical vapor deposition, chemical vapor deposition, or a transfer method.

Description

BRIEF DESCRIPTION OF THE DRA WINGS

[0019] FIG. 1A to FIG. 1G are schematic cross-sectional diagrams of a manufacturing process of a semiconductor device according to an example of the invention.

[0020] FIG. 2 is an SEM image of a two-dimensional semiconductor device of an experimental example.

[0021] FIG. 3A is an Id-Vg curve of a two-dimensional semiconductor device of an experimental example.

[0022] FIG. 3B is an Id-Vd curve of a two-dimensional semiconductor device of an experimental example.

[0023] FIG. 4A to FIG. 4B are electrical analysis diagrams of an experimental 2D semiconductor device of an experimental example using <Electrical analysis 2> method.

[0024] FIG. 5A is a bar chart of the ON/OFF current ratio (I.sub.onoff ratio) of a two-dimensional semiconductor device of an experimental example.

[0025] FIG. 5B is a bar chart of the threshold voltage of a two-dimensional semiconductor device of an experimental example.

[0026] FIG. 5C is a bar chart of the subthreshold swing of a two-dimensional semiconductor device of an experimental example.

[0027] FIG. 5D is an Ion bar chart of a two-dimensional semiconductor device of an experimental example.

[0028] FIG. 5E is a mobility bar chart of a two-dimensional semiconductor device of an experimental example.

[0029] FIG. 6A is an TEM image of a two-dimensional semiconductor device of an experimental example.

[0030] FIG. 6B is an HR-TEM image (dark field) of FIG. 6A.

[0031] FIG. 7A is another TEM image of a two-dimensional semiconductor device of an experimental example.

[0032] FIG. 7B is an HR-TEM image (bright field) of FIG. 7A.

DESCRIPTION OF THE EMBODIMENTS

[0033] The following content provides several examples for implementing different features of the invention. However, the examples are only exemplary and are not intended to limit the scope and application of the invention. Furthermore, relative dimensions (such as length, spacing, etc.) and relative positions of various components or structures may be scaled up or down for clarity.

[0034] FIG. 1A to FIG. 1G illustrate cross-sectional schematics of a semiconductor device manufacturing process, according to an embodiment of the invention.

[0035] In FIG. 1A, in the present embodiment, a substrate 100 includes monocrystalline, polycrystalline, or amorphous silicon or germanium which have a first dielectric material layer 102 and a second dielectric material layer 103.

[0036] In some embodiments, the substrate 100 is made of a compound semiconductor, such as silicon germanium (SiGe), gallium nitride (GaN), indium phosphide (InP), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide, an amorphous oxide semiconductor like InGaZnO, or a combination thereof. The substrate 100 may also include a single layer or several layers of an insulator, a metal, a semiconductor, a semiconductor on insulator (SOI), or a combination thereof.

[0037] In FIG. 1B, a two-dimensional semiconductor layer 104 is formed on the substrate 100, wherein the material of the two-dimensional semiconductor layer 104 may be selected from the transition metal dichalcogenide family (TMDC), such as tungsten disulfide (WS.sub.2), molybdenum disulfide (MoS.sub.2), tungsten diselenide (WSe.sub.2), etc., or compound semiconductor materials having a layered structure, such as Bi.sub.2O.sub.2Se, InSe, GaSe, etc. The layer is deposited by PVD, CVD, or transferred using a transfer method. The two-dimensional semiconductor layer 104 generally has an extremely small thickness and a relatively greater area.

[0038] In FIG. 1C, a protective layer 106 is deposited on the two-dimensional semiconductor layer 104, wherein the material of the protective layer 106 may be selected from dielectric materials such as oxide or nitride, such as aluminum oxide (Al.sub.2O.sub.3), silicon oxide (SiO.sub.2), aluminum nitride (AlN), silicon nitride (Si.sub.3N.sub.4), silicon oxynitride (SiON), or a combination of the above.

[0039] In FIG. 1D, the protective layer 106 and the two-dimensional semiconductor layer 104 are patterned to define an active area (AA) of the device. In the present embodiment, the method of patterning the protective layer 106 and the two-dimensional semiconductor layer 104 involves forming a patterned photoresist (PR) on the protective layer 106 using one or more photolithography processes. The unprotected portions of the protective layer 106 and the two-dimensional semiconductor layer 104 are subsequently removed using a dry etching technique, such as inductively coupled plasma (ICP), remote plasma, capacitor-coupled plasma (CCP), atomic layer etching (ALE), or a wet etching technique, such as buffer oxide etchant (BOE), phosphoric acid (H.sub.3PO.sub.4), sodium hydroxide (NaOH), or potassium hydroxide (KOH).

[0040] In particular, the composition of dry etching plasma gas includes a combination of water vapor (H.sub.2O), oxygen (O.sub.2), boron chloride (BCl.sub.3), chlorine (Cl.sub.2), argon (Ar), nitrogen fluoride (NF.sub.3), hydrogen bromide (HBr), sulfur fluoride (SF.sub.6), CH.sub.2F.sub.2, and CH.sub.4.

[0041] In FIG. 1E, a patterned photoresist is removed, and the electrodes E1 and E2 are deposited on the protective layer 106 and substrate 100. Formation of the first electrode E1 and the second electrode E2 includes depositing a single layer or several layers of a metal film using chemical or physical vapor deposition, and removing a portion of the metal film via etching. The structure of the first electrode E1 and the second electrode E2 may be a combination of TiN/Ti/TiN, Ta/TiN, TiAlC, WN, Ni, Ti, tungsten, molybdenum, cobalt, etc. or a single-layer or multi-layer structure thereof. It should be noted that the invention is not limited to these materials or combinations.

[0042] The protective layer shields the two-dimensional semiconductor layer 104 from damage during process, allowing flexibility in materials and the deposition option of the first electrode E1 and the second electrode E2.

[0043] In an embodiment, the first electrode E1 may be used as the source of the semiconductor device, the second electrode E2 may be used as the drain of the semiconductor device, and the two-dimensional semiconductor layer 104 may be used as a channel of the semiconductor device.

[0044] In FIG. 1F, the protective layer 106 in FIG. 1E is completely removed, so that the first electrode E1 and the second electrode E2 are collapsed onto the surface of the two-dimensional semiconductor layer 104, forming a van der Waals gap 108 between the first electrode E1 and the two-dimensional semiconductor layer 104 and between the second electrode E2 and the two-dimensional semiconductor layer 104.

[0045] In FIG. 1G, the collapsed first electrode E1 and second electrode E2 form a van der Waals contact structure (VC) between the first electrode E1 and the two-dimensional semiconductor layer 104 and between the second electrode E2 and the two-dimensional semiconductor layer 104.

[0046] Several experimental examples are listed below to verify the implementation of the invention, but the invention is not limited to the following contents.

<Experimental Example> Fabrication of Two-Dimensional Semiconductor Device.

[0047] First, a silicon oxide layer and a hafnium oxide (HfO.sub.2) layer were formed on a silicon wafer. Then, a molybdenum disulfide film was deposited, and an aluminum oxide layer was deposited on the surface of the molybdenum disulfide film using an electron gun (E-Gun) evaporation. Then, a photolithography process was performed using an Canon FPA-6300es6a scanner, and a portion of the aluminum oxide layer and the molybdenum disulfide film was removed using a BOE solution to define the active area of the device. The remaining molybdenum disulfide film was used as a channel of the transistor, with a channel length of approximately 200 nm and a channel width of approximately 1 m. Then, metal films were formed via sputtering, wherein the metal films were titanium nitride/titanium/titanium nitride (TiN/Ti/TiN) using ULVAC ENTRON W200. Then, a first electrode and a second electrode were defined using a Lam Research 2300 etcher. Lastly, the aluminum oxide layer was removed completely using the BOE solution, so that the first electrode E1 and the second electrode E2 were collapsed onto the surface of the molybdenum disulfide film to complete the fabrication of the transistor device.

[0048] FIG. 2 is a scanning electronic microscopy (SEM) image of a two-dimensional semiconductor device of an experimental example, wherein the positional relationship between the first electrode E1, the second electrode E2, and the two-dimensional semiconductor layer 104 (molybdenum disulfide film) is shown.

<Electrical Analysis 1>

[0049] FIG. 3A and FIG. 3B depict electrical characteristics of the experimental device, showing transfer and output characteristics which is the electrical characteristics of a transistor. In addition, the IV curve in FIG. 3B for which Vgs is 0 V is not drawn specifically since the transistor is in the off state and Ids is fixed at 0.

<Electrical Analysis 2>

[0050] According to the method of the experimental example, 218 independent two-dimensional semiconductor devices were fabricated in a single die on an eight-inch wafer.

[0051] In order to ensure that the standards for determining device characteristics were consistent every time and to reduce determination errors caused by measurement as much as possible, the inventors established a SPICE (Simulation Program with Integrated Circuits Emphasis) model for two-dimensional semiconductor materials, which was used to systematically, quickly, and effectively extract transistor parameters.

[0052] First, transition metal sulfides are inherently easy to desorb on the material surface due to chalcogen elements, forming vacancies (chalcogen vacancy). The resulting defect energy state density (gap state) may be observed from the band relationship. Since the position thereof is close to the lowest point of the conduction band (conduction band minimum, CBM), this material is similar to an n-type semiconductor having a certain doping concentration. The two-dimensional semiconductor material transistor made on this basis is operated in a depletion mode, and the carriers become an n-type accumulation model with the change in the surface band bending.

[0053] In equation (2.182) in the reference document (Fundamentals of Modern VLSI Devices (2nd ed.) published in 2009, author/editor Yuan Taur & Tak H. Ning, Cambridge: Cambridge University Press), it may be deduced through the principle of electrical neutrality and Poisson's equation that the charge density (Qs) and the surface band bending (S) of n-type semiconductor materials have the following relationship:

[00001]$\begin{array}{cc}{Q}_S={\sqrt{2{}_{S}kT{N}_d}\left[\left(e^{\frac{q{}_S}{kT}}-\frac{q{}_S}{kT}-1\right)+\frac{n_i^2}{N_d^2}\left(e^{\frac{-q{}_S}{kT}}+\frac{q{}_S}{kT}-1\right)\right]}^{1/2}& \left(1\right)\end{array}$

[0054] Referring to the equation (2.202) in the above literature, it may be derived that the ideal gate electric field is across the dielectric layer material and the semiconductor material respectively, and is described by the following equation:

[00002]$\begin{array}{cc}{V}_g=\frac{q{N}_d{t}_{ox}}{{}_S{}_0}\sqrt{\frac{2{}_S{}_0}{q{N}_d}}\sqrt{{}_S}+{}_S=A\sqrt{{}_S}+{}_S& \left(2\right)\end{array}$

wherein the dielectric layer cross-voltage is the first mathematical relationship that may be expressed by the degree of semiconductor surface band bending, and the fixed parameter value of the basic material parameter is represented by A to obtain a simplified mathematical relationship.

[0055] This simplified mathematical relationship is a quadratic equation of one variable, wherein Us may be converted into the following relationship:

[00003]$\begin{array}{cc}{}_S=\frac{A^2\sqrt{A^4+4A^2{V}_g}+2V_g}{2}& \left(3\right)\end{array}$

[0056] At this time, this relationship is brought into equation (1), and the material charge density may be expressed by applying a bias voltage to the gate. Since the two-dimensional material is an n-type accumulation model and the current size is proportional to the surface charge density and most of the parameter terms are simplified and the translation correction term is taken into account, equation (1) may be simplified into the following relationship:

[00004]$\begin{array}{cc}{Q}_S=A^{}{e}^{\left(B\left(C\sqrt{V_g}\right)+2V_g\right)}+D& \left(4\right)\end{array}$

[0057] The transistor current is proportional to Qs, so A may be replaced with another parameter to obtain the actual current.

[0058] After the basic transistor model is established, data fitting may be started. There are four parameter items in equation (4) that may be used for curve adjustment. The process continuously iterates the values of the four parameters and measures the errors with the experimental values. Lastly, a fitting curve with the smallest error (local minimum) from the experimental values is obtained. Then, the device parameters are extracted based on this fitting curve to obtain five basic parameters of transistors such as transistor current on/off ratio, threshold voltage (Vth), subthreshold swing (S.S), Ion (maximum current density), and carrier mobility (eff).

[0059] The following are the steps of the analysis program written by the inventors using MATLAB mathematics software: [0060] Step 1. Data was collected and classified (position, device size . . . ) [0061] Step 2. The current on/off ratio was determined using a Sigmoid Function (S-shaped function) fitting curve. [0062] Step 3. A current on/off ratio of the device less than 102 (A/A) was determined as failure. [0063] Step 4. Ioff data was discarded. [0064] Step 5. The curve was fitted using a two-dimensional material SPICE model and an n-type accumulation model was obtained, such as the curve of FIG. 4A. [0065] Step 6. The curve of FIG. 4A was exponentially converted into a linear relationship to obtain a line segment as shown in FIG. 4B, wherein the point where the tangent line is intersected with the X-axis is the Vth value. [0066] Step 7. The linear relationship data was differentiated to obtain gm (transduction) and eff values. [0067] Step 8. The maximum current density was calculated according to different device design sizes. [0068] Step 9. The data was classified and summarized (characteristic and positional relationship diagram, normal distribution diagram, data classification quantity diagram, transistor output current diagram, transistor transfer curve diagram).

[0069] FIG. 5A to FIG. 5E are bar charts of current on/off ratio, threshold voltage, subthreshold swing. Ion, and mobility obtained according to the above method.

[0070] It may be seen from FIG. 5A that most two-dimensional semiconductor devices have a current on/off ratio exceeding the five order (the numbers of the horizontal axis of FIG. 5A represent powers of 10). Moreover, after further statistics, it is found that about 83% of the two-dimensional semiconductor devices have a current on/off ratio exceeding the fifth power, and 95% of the two-dimensional semiconductor devices have a current on/off ratio exceeding the four order. This result represents a yield rate of 83% or more.

[0071] It may be seen from FIG. 5B that the statistically obtained threshold voltage is about 15 V.

[0072] It may be seen from FIG. 5C that the statistically obtained subthreshold swing is about 900 mV/dev.

[0073] It may be seen from FIG. 5D that the statistically obtained Ion is about 0.8 A/m.

[0074] It may be seen from FIG. 5E that the statistically obtained mobility is about 1 cm.sup.2/V-sec.

[0075] The values obtained by the above statistics are all consistent with the electrical characteristics of the transistor and have excellent yield.

<Physical Analysis>

[0076] FIG. 6A is a transmission electron microscopy (TEM) image of a two-dimensional semiconductor device of an experimental example. FIG. 6B is a high-resolution transmission electron microscopy (HR-TEM) image (dark field) of FIG. 6A.

[0077] FIG. 7A is another TEM image of a two-dimensional semiconductor device of an experimental example. FIG. 7B is an HR-TEM image (bright field) of FIG. 7A.

[0078] It may be seen from the TEM images of FIG. 6A and FIG. 7A that the two-dimensional semiconductor layer (MoS.sub.2) is still intact after the entire process and shows good contact with the metal film (electrode). It may be further observed from the HR-TEM images of FIG. 6B and FIG. 7B that the metal-semiconductor junction (the interface between MoS.sub.2 and the electrode) has a very narrow gap, indicating a van der Waals contact structure, which is expected to effectively improve the performance of the two-dimensional semiconductor layer.

[0079] Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.