An etchant composition and a method of fabricating a semiconductor device, the composition including an inorganic acid; about 0.01 parts by weight to about 0.5 parts by weight of colloidal silica; about 0.01 parts by weight to about 30 parts by weight of an ammonium-based additive; and about 20 parts by weight to about 50 parts by weight of a solvent, all parts by weight being based on 100 parts by weight of the inorganic acid.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

A high-voltage transistor includes an asymmetric gate dielectric layer and/or a gate structure that includes one or more asymmetric work function metal layers. The gate dielectric layer and/or the work function metal layer(s) are asymmetric in that the height of the gate dielectric layer and/or the height of the work function metal layer(s) on opposing sides of the gate structure are different. In particular, the height of the gate dielectric layer and/or the height of the work function metal layer(s) on a side of the gate structure facing the drain region of the high-voltage transistor are lower than the height of the gate dielectric layer and/or the height of the work function metal layer(s) on an opposing side of the gate structure facing the source region of the high-voltage transistor.

Molybdenum is etched in a highly controllable manner by performing one or more etch cycles, where each cycle involves exposing the substrate having a molybdenum layer to an oxygen-containing reactant to form molybdenum oxide followed by treatment with boron trichloride to convert molybdenum oxide to a volatile molybdenum oxychloride with subsequent treatment of the substrate with a fluorine-containing reactant to remove boron oxide that has formed in a previous reaction, from the surface of the substrate. In some embodiments the method is performed in an absence of plasma and results in a substantially isotropic etching. The method can be used in a variety of applications in semiconductor processing, such as in wordline isolation in 3D NAND fabrication.

Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.

Disclosed is a plasma etching method. The method may include a first step of vaporizing liquid heptafluoroisopropyl methyl ether (HFE-347mmy) and liquid pentafluoropropanol (PFP); a second step of supplying a discharge gas containing the vaporized HFE-347mmy, the vaporized PFP, and argon gas to a plasma chamber in which an etching target is disposed; and a third step of discharging the discharge gas to generate plasma and of plasma-etching the etching target using the generated plasma.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

A method for manufacturing an SOI wafer including a step of performing an adjustment to a film thickness of an SOI layer of the SOI wafer by wet etching. In the step of performing the adjustment to the film thickness of the SOI layer, a first etching step of etching a surface of the SOI layer using an SC1 solution; and a second etching step of etching the surface of the SOI layer by bringing the SOI layer into contact with ozone water to form an oxide film on the surface of the SOI layer and then bringing the formed oxide film into contact with an HF-containing aqueous solution to remove the oxide film, are performed in combination. The etchings are performed such that a removal amount of the SOI layer in the first etching step is smaller than that in the second etching step.

The present application discloses a support bracing structure, a semiconductor device with the support bracing structure, and a method for fabricating the semiconductor device with the support bracing structure. The support bracing structure includes a first bracing layer including two connection portions respectively positioned on top surfaces of two adjacent bottom electrodes, and a frame portion bridging the two connection portions; and a protection layer including a first portion positioned on and conforming to an inner surface of the frame portion and positioned between the two connection portions. The inner surface of the frame portion is normal to the top surfaces of the two adjacent bottom electrodes.