An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include removing at least a portion of the metal-containing hardmask material.

The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

A technique improves etch selectivity. An etching includes (a) providing, in a chamber, a substrate including an underlying film and a silicon-containing film on the underlying film, (b) etching the silicon-containing film to form a recess with first plasma generated from a first process gas containing a hydrogen fluoride gas until before the underlying film is exposed at the recess or until the underlying film is partly exposed at the recess, and (c) further etching the silicon-containing film at the recess under a condition different from a condition of (b).

A process for forming a device can include forming a first semiconductor region having a first conductivity type. The process can include depositing a dielectric layer over the first semiconductor region, the dielectric layer having a first etch rate. The process can include forming a first photoresist layer having a second etch rate that is greater than the first etch rate over the dielectric layer and forming a second photoresist layer over the first photoresist layer. The process can include patterning the second photoresist layer to remove a region of the second photoresist, the first photoresist layer being exposed under the region. The process can include etching to form a beveled structure in the dielectric layer. The process can include removing the first photoresist layer and the second photoresist layer and performing ion implantation of the first semiconductor region with dopant species having a second conductivity type.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

A method includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. The method includes forming a metal layer over the dielectric layer. The method includes forming a patterned mask over the metal layer. The method includes performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer. The method further includes performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns.