A manufacturing method of a semiconductor device includes depositing a first bilayer structure over a substrate, in which the first bilayer structure includes a silicon oxide layer and a silicon nitride layer over the silicon nitride layer; forming a first carbonaceous hard mask on the first bilayer structure; forming a second bilayer structure on the first carbonaceous hard mask; forming a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbonaceous hard masks on the second bilayer structure; and coating a photoresist on the mask stack.

A manufacture includes a polysilicon structure over a portion of a substrate. The manufacture further includes a spacer on a sidewall of the polysilicon structure, wherein the spacer has a concave corner region between an upper portion and a lower portion, the spacer has an outer sidewall and an inner sidewall, and the inner sidewall is between the outer sidewall and the polysilicon structure. The manufacture further includes a protective layer exposing a portion of the outer sidewall of the spacer above the concave corner region, wherein the protective layer covers an entirety of the lower portion of the spacer, and the protective layer directly contacts the substrate.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

A substrate processing method is provided and includes forming a laminated structure film over a substrate, the laminated structure film including a metal-containing layer and a halogen-containing layer that are laminated; irradiating the laminated structure film with extreme ultraviolet light in a predetermined pattern to form, in the laminated structure film, an exposed portion irradiated with the extreme ultraviolet light and an unexposed portion not irradiated with the extreme ultraviolet light; and selectively removing the exposed portion of the laminated structure film.

The present disclosure provides a method for improving residue formation after mandrel removal, including steps of: providing a TEOS layer, forming mandrel structures spaced apart from each other on the TEOS layer, and forming spacers on sidewalls of each of the mandrel structures; forming a first SOC layer to cover the surface of the TEOS layer, the mandrel structures, and the spacers of the mandrel structures, and forming a SOC structure that covers the spacers and exposes the top surfaces of the mandrel structures; removing the mandrel structures by etch along sidewalls of SOC structure, forming a first groove between two of the spacers on the sidewalls of the removed mandrel structures; forming a second SOC layer to cover the SOC structure and fill the first groove; performing top planarization of the second SOC layer until the top surface of the SOC structure is exposed.

Provided are methods of manufacturing memory devices. The methods include exposing a film stack to an etching gas to remove alternating sacrificial layers of silicon nitride in the film stack. The memory devices have alternating layers of silicon oxide and silicon nitride and an opening formed therein. The etching gas comprises derivatives of phosphoric acid, phosphonic acid, and phosphonic acid. The silicon nitride layers are selectively etched relative to the silicon oxide layers with improved isotropicity and without compromising the integrity of the film stack.

Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. In an example, a method includes receiving a plurality of adjoining structures over a substrate. The structures comprise first and second outer sidewalls comprising a first material. An inner material and an intervening material is between the first and second outer sidewalls. The inner material is recessed with a first etch to a recess depth. A surface of the first or second outer sidewall is revealed to the recess depth by etching the intervening material with a second etch.