A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: regions of direct contact between the working layer and the carrier substrate; and agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.

A memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store a data bit; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells. The data bit stored by a first one of the plurality of memory cells presents a first logic state when the first memory cell includes a first channel structure, with a first end and a second end of the first channel structure connected to a first epitaxial structure and a second epitaxial structure, respectively, and wherein the first epitaxial structure is overlaid by a dielectric structure and the second epitaxial structure is overlaid by a first contact structure.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a high resistance impedance layer between a gate and a first metal structure in a vertical direction, wherein the first metal structure comprises at least one equipotential first metal and at least one non-equipotential first metal, wherein the equipotential first metal and the high resistance impedance layer have the same potential, the non-equipotential first metal and high resistance impedance layer have not the same potential, and the non-equipotential first metal and the high resistance impedance layer do not overlap in the vertical direction, and a minimum distance, between an edge of the high resistance impedance layer and an edge of the non-equipotential first metal in a horizontal direction perpendicular to the vertical direction, is larger than a size of a random defect.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

The present disclosure relates to semiconductor processing including epitaxial growth of a semiconductor material, and more particularly for some examples, to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a device includes a semiconductor substrate, a pedestal dielectric stack over the substrate, and a BJT on the substrate. The pedestal dielectric stack includes nitrogen at an interface between first and second sub-layers of the pedestal dielectric stack. An opening is through the pedestal dielectric stack to the substrate. The opening is defined at least in part by a retrograde sidewall, which is retrograde into the pedestal dielectric stack from distal from the substrate to proximate the substrate. At least a first portion of the BJT is on an upper surface of the substrate and in the opening through the pedestal dielectric stack. At least a second portion of the BJT is over the pedestal dielectric stack.

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm.Math.cm and a thickness greater than 5 microns positioned on the first insulating layer.

Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.