A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

In a temperature regulation unit (10), a flow passage (50) for a fluid is formed between a plurality of rod-shaped members (30) which extend parallel to each other so as to be spaced apart from each other and are formed from porous metal; in the flow passage (50), the fluid flows along a flow direction which is a direction orthogonal to a direction in which the rod-shaped members (30) extend; and the flow passage (50) meanders along the flow direction.

In examples, an electronic device comprises a multi-layer substrate including multiple metal layers and a solid dielectric layer positioned between the multiple metal layers, the multi-layer substrate including first and second contacts coupled to the multiple metal layers. The electronic device comprises a semiconductor die having a first surface coupled to the multi-layer substrate and a second surface opposite the first surface, and a passive component having a conductive terminal coupled to the first contact. The electronic device includes a first thermally conductive component contacting the second surface of the semiconductor die and contacting the second contact, the first thermally conductive component positioned between the semiconductor die and the passive component. The electronic device includes a second thermally conductive component coupled to the first thermally conductive component, the second thermally conductive component circumscribing the passive component.

A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

The present disclosure provides a package structure. The package structure includes: a first die having a front surface and a back surface opposite to the front surface; and a first thermal management structure over the back surface. The first thermal management structure includes: a first copper-phosphorous alloy layer thermally coupled to and covering an entirety of the back surface of the first die.

The present disclosure provides a package structure. The package structure includes: a first die having a first front surface and a first back surface opposite to the first front surface; a second die having a second front surface and a second back surface opposite to the second front surface, wherein the first back surface faces the first front surface; and a first thermal management structure over the first back surface. The first thermal management structure includes a first copper-phosphorous alloy layer thermally coupled to the first back surface.

The electronic device includes a semiconductor module provided on a heat sink including a first joined surface portion. The semiconductor module includes a heat dissipation plate including a second joined surface portion joined to the first joined surface portion via a thermally-conductive bonding material, and a transistor chip placed on a side of the heat dissipation plate which is opposite to the second joined surface portion. At least one joined surface portion out of the first joined surface portion and the second joined surface portion includes a plurality of protrusions protruding toward the other joined surface portion out of the first joined surface portion and the second joined surface portion, a first recess placed between the protrusions and recessed in a direction away from the other joined surface portion, and a second recess placed outward of the plurality of protrusions and recessed in a direction away from the other joined surface portion. A thickness at the first recess of the thermally-conductive bonding material is greater than a thickness at the protrusions thereof, and a thickness at the second recess of the thermally-conductive bonding material is greater than the thickness at the first recess.

In one example, an electronic device comprises a substrate having a first conductive structure, an electronic component coupled to the first conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects around the electronic component, wherein the vertical interconnects are coupled to the first conductive structure at the first side of the substrate, an interposer having a second conductive structure coupled to the plurality of vertical interconnects, a thermal body coupled between the electronic component and the interposer, and an encapsulant between the substrate and the interposer, around the thermal body, around the plurality of vertical interconnects, and around the electronic component. Other examples and related methods are also disclosed herein.

A thermal interface layer includes pluralities of first and second particles dispersed in a polymeric binder at a total loading V in a range of about 40 volume percent to about 70 volume percent. The first and second particles have different compositions. The first particles include one or more of iron or nickel. The second particles include one or more of aluminum, magnesium, silicon, copper, or zinc. The thermal interface layer has a thermal conductivity in a thickness direction of the thermal interface layer in units of W/mK of at least K=5.10.17 V+0.002 V.sup.2.