Provided in the present application are a chip packaging structure and a preparation method therefor. The chip packaging structure comprises a substrate, a chip, an insulating layer, a capacitor structure and a packaging layer. According to the chip packaging structure and the packaging method therefor provided in the present application, a capacitor structure is packaged on a surface and a lateral wall of a chip, such that the capacitor structure is applied in packaging, thereby improving the level of integration of the chip. In the present application, a first electrode layer, a second electrode layer and a capacitive dielectric layer all extend along a surface on a side of a chip facing away from a substrate and along a lateral wall of the chip. Therefore, a larger relative area of the first electrode layer and the second electrode layer can be obtained, which can improve the capacity of a capacitor.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a package includes first and second IC dice. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is on a substrate. The capacitor includes a bottom plate over the substrate and a top plate over the bottom plate. The polyimide layer is at least partially over the top plate. A distance from a top surface of the top plate to a bottom surface of the polyimide layer is at least 30% of a distance from a top surface of the bottom plate to a bottom surface of the top plate. A signal path, including the capacitor, is electrically coupled between the first circuit and a second circuit in the second IC die, which does not include a galvanic isolation capacitor in the signal path.

The device may include a core. The device may include built-up layers arranged over the core. The device may also include a ground path disposed in a first built-up layer of the built-up layers. The device may also include a power path disposed in a second built-up layer of the built-up layers. The device may also include a multi-terminal capacitor on a top layer of the built-up layers. The multi-terminal capacitor may be coupled to the ground path and the power path through respective vias passing through the built-up layers. The respective vias may be arranged to alternate such that respective vias coupled to the power path neighbor a respective via coupled to the ground path.

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package, a first adhesive and a second adhesive. The substrate has a first board surface and a second board surface, and a second region surrounds a first region on the first board surface. The semiconductor package has an upper surface, a lower surface, and a side surface, and is disposed on the first board surface. The first adhesive is formed on the first board surface, in the second region and in a portion of the first region adjacent to the second region. The second adhesive is formed between the side surface and the first adhesive and contacts the side surface and the first adhesive, and the first adhesive and the second adhesive together form a pier adhesive.

A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package, a first adhesive and a second adhesive. The substrate has a first board surface and a second board surface, and a second region surrounds a first region on the first board surface. The semiconductor package has an upper surface, a lower surface, and a side surface, and is disposed on the first board surface. The first adhesive is formed on the first board surface, in the second region and in a portion of the first region adjacent to the second region. The second adhesive is formed between the side surface and the first adhesive and contacts the side surface and the first adhesive, and the first adhesive and the second adhesive together form a pier adhesive.